ST10F280 datasheet(132/186 Pages) STMICROELECTRONICS

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ST10F280

When enabled, the open drain of the RSTIN pin is

activated, pulling down the reset signal, for the

duration

the

internal

reset

sequence

(synchronous/asynchronous hardware, software

and watchdog timer resets). At the end of the

internal reset sequence the pull down is released

and the RSTIN pin is sampled 8 TCL periods later.

– If signal is sampled low, a hardware reset is trig-

gered again.

– If it is sampled high, the chip exits reset state ac-

cording to the running reset way (synchronous/

asynchronous hardware, software and watch-

dog timer resets ).

Note: The bidirectional reset function is disabled

any

reset

sequence

(Bit

BDRSTEN

SYSCON is cleared). To be activated again it must

be enabled during the initialization routine.

17.6 - Reset Circuitry

The internal reset circuitry is described in Figure

68.

An internal pull-up resistor is implemented on

RSTIN pin. (50k

Ω minimum, to 250kΩ maximum).

The minimum reset time must be calculated using

the lowest value.

In addition, a programmable

pull-down (bit BDRSTEN of

SYSCON register)

drives the RSTIN pin according to the internal

reset state as explained in Section 17.5 -

RSTOUT Pin and Bidirectional Reset.

The RSTOUT pin provides a signals to the

application

as described

Section 17.5

RSTOUT Pin and Bidirectional Reset.

A weak internal pull-down is connected to the

RPD pin to discharge external capacitor to Vss at

a rate of 100

µA to 200µA. This Pull-down is

turned on when RSTIN pin is low

If bit PWDCFG of SYSCON register is set, an

internal pull-up resistor is activated at the end of

the reset sequence. This

pull-up charges the

capacitor connected to RPD pin.

If Bidirectional Reset function is not used, the

simplest way to reset ST10F280 is to connect

external components as shown in Figure 69. It

works with

reset from application (hardware or

manual) and with power-on. The value of C1

capacitor, connected on RSTIN pin with internal

pull-up resistor (50k

Ω to 250kΩ), must lead to a

charging time long enough to let the internal or

external oscillator and / or the on-chip PLL to

stabilize.

The R0-C0 components on RPD pin are mainly

implemented to provide a time delay to exit Power

down mode (see Chapter 18 - Power Reduction

Modes). Nervertheless, they drive RPD pin level

during resets and they lead to different reset

modes as explained hereafter. On power-on, C0

is totaly discharged, a low level on RPD pin forces

an asynchronous hardware reset. C0 capacitor

starts to charge throught R0 and at the end of

reset sequence ST10F280 restarts. RPD pin

threshold is typically 2.5V.

Depending on the delay of the next applied reset,

the MCU can enter a synchronous reset or an

asynchronous reset. If RPD pin is below 2.5V an

asynchronous reset starts, if RPD pin is above

2.5V

a synchronous reset starts. (see Section

17.1 - Asynchronous Reset (Long Hardware

Reset) and Section 17.2 - Synchronous Reset

(Warm Reset)).

Note that an internal pull-down is connected to

RPD pin and can drive a 100

µA to 200µA current.

This Pull-down is turned on when RSTIN pin is

low.

In order to properly use the Bidirectional reset

features, the schematic (or equivalent) of Figure

70 must be implemented. R1-C1 only work for

power-on or manual reset in the same way as

explained previously. D1 diode brings a faster

discharge of C1 capacitor at power-off during

repetitive switch-on / switch-off sequences. D2

diode performs an OR-wired connection, it can be

replaced with an open drain buffer. R2 resistor

may be added to increase the pull-up current to

the open drain in order to get a faster rise time on

RSTIN pin when bidirectional function is activated.

The start-up configurations and some system

features are selected on reset sequences as

described in Table 33 and Table 34.

Table 33

describes

what

the

system

configuration latched on PORT0 in the five

different reset ways. Table 34 summarizes the bit

state of PORT0 latched in RP0H, SYSCON,

BUSCON0 registers. RPOH register is described

in Section 19.2 - System Configuration Registers.

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