ST10F280 datasheet(130/186 Pages) STMICROELECTRONICS

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ST10F280

17.2 - Synchronous Reset (Warm Reset)

A synchronous reset is triggered when RSTIN pin

is pulled low while RPD pin is at high level. In

order to properly activate the internal reset logic of

the MCU, the RSTIN pin must be held low, at least,

during 4 TCL (2 periods of CPU clock). The I/O

pins are set to high impedance and RSTOUT pin is

driven low. After RSTIN level is detected, a short

duration of 12 TCL (approximately 6 periods of

CPU clock) elapes, during which pending internal

hold states are cancelled and the current internal

access cycle if any is completed. External bus

cycle is aborted. The internal pull-down of RSTIN

pin is activated if bit BDRSTEN of

SYSCON

always cleared on power-on or after a reset

sequence.

Exit of synchronous reset state

The internal reset sequence starts for 1024 TCL

(512 periods of CPU clock) and RSTIN pin level is

sampled. The reset sequence is extended until

RSTIN level becomes high. Then, the MCU

restarts. The system configuration is latched from

PORT0 and ALE, RD and R/W pins are driven to

their inactive level. The MCU starts program

execution from memory location 00'0000h in code

segment 0. This starting location will typically

point to the general initialization routine. Timing of

synchronous reset sequence are summarized in

Figure 66 and Figure 67.

Notes: 1. RSTIN assertion can be released there.

2. If during the reset condition (RSTIN low), VRPD voltage drops below the threshold voltage (about 2.5V for 5V operation), the

asynchronous reset is then immediately entered.

3. RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on

(fCPU =fXTAL / 2), else it is 4 CPU clock cycles (8 TCL).

4) RSTIN pin is pulled low if bit BDRSTEN (bit 5 of SYSCON register) was previously set by software. Bit BDRSTEN is cleared after

reset.

Figure 66 : Synchronous Warm Reset (Short low pulse on RSTIN)

CPU Clock

RSTIN

RPD

RSTOUT

ALE

PORT0

INST #1

Internal

Reset

Signal

Latching point of PORT0

for system start-up configuration

6 or 8 TCL3

4 TCL

12 TCL

min.

max.

1024 TCL

Internally pulled low4

Reset Configuration

VRPD > 2.5V Asynchronous Reset not entered.

200

µA Discharge

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