ST10F280 datasheet(166/186 Pages) STMICROELECTRONICS

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ST10F280

166/186

Note: 1. Partially tested, guaranted by design characterization.

t42

ALE fall. edge to RdCS, WrCS

(with RW delay)

7 + tA

–

TCL - 5.5+ tA

–ns

t43

ALE fall. edge to RdCS, WrCS

(no RW delay)

-5.5 + tA

–

-5.5 + tA

–ns

t44

Address float after RdCS,

WrCS (with RW delay)

–0

–

t45

Address float after RdCS,

WrCS (no RW delay)

–

12.5

–

TCL

t46

RdCS to Valid Data In

(with RW delay)

–4 + tC

–

2 TCL - 21 + tC

t47

RdCS to Valid Data In

(no RW delay)

–

16.5 + tC

–

3 TCL - 21 + tC

t48

RdCS, WrCS Low Time

(with RW delay)

15.5 + tC

–

2 TCL - 9.5 + tC

–ns

t49

RdCS, WrCS Low Time

(no RW delay)

28 + tC

–

3 TCL - 9.5 + tC

–ns

t50

Data valid to WrCS

10 + tC

–

2 TCL - 15+ tC

–ns

t51

Data hold after RdCS

0–

–

t52

Data float after RdCS

–

16.5 + tF

–

2 TCL - 8.5+tF

t54

Address hold after

RdCS, WrCS

6 + tF

–

2 TCL - 19 + tF

–ns

t56

Data hold after WrCS

6 + tF

–

2 TCL - 19 + tF

–ns

Table 41 : Multiplexed Bus Characteristics

Symbol

Parameter

Max. CPU Clock

= 40MHz

Variable CPU Clock

1/2 TCL = 1 to 40MHz

min.

max.

min.

max.

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