ST10F280 datasheet(165/186 Pages) STMICROELECTRONICS

165 / 186 page

ST10F280

165/186

20.4.10 - Multiplexed Bus

VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF,

ALE cycle time = 6 TCL + 2tA + tC + tF (75ns at 40MHz CPU clock without wait states).

Table 41 : Multiplexed Bus Characteristics

Symbol

Parameter

Max. CPU Clock

= 40MHz

Variable CPU Clock

1/2 TCL = 1 to 40MHz

min.

max.

min.

max.

ALE high time

4 + tA

–

TCL - 8.5 + tA

–ns

Address setup to ALE

2 + tA

–

TCL - 10.5 + tA

–ns

Address hold after ALE

4 + tA

–

TCL - 8.5 + tA

–ns

ALE falling edge to RD, WR

(with RW-delay)

4 + tA

–

TCL - 8.5 + tA

–ns

ALE falling edge to RD, WR (no

RW-delay)

-8.5 + tA

–

-8.5 + tA

–ns

t10

Address float after RD, WR

(with RW-delay)

–6

–

t11

Address float after RD, WR

(no RW-delay)

–

18.5

–

TCL + 6

t12

RD, WR low time

(with RW-delay)

15.5 + tC

–

2 TCL -9.5 + tC

–ns

t13

RD, WR low time

(no RW-delay)

28 + tC

–

3 TCL -9.5 + tC

–ns

t14

RD to valid data in

(with RW-delay)

–6 + tC

–

2 TCL - 19 + tC

t15

RD to valid data in

(no RW-delay)

–

18.5 + tC

–

3 TCL - 19 + tC

t16

ALE low to valid data in

–

18.5

+ tA + tC

–

3 TCL - 19

+ tA + tC

t17

Address/Unlatched CS to valid

data in

–

22 + 2tA +

–

4 TCL - 28

+ 2tA + tC

t18

Data hold after RD

rising edge

0–

–

t19

Data float after RD

–

16.5 + tF

–

2 TCL - 8.5 + tF

t22

Data valid to WR

10 + tC

–

2 TCL -15 + tC

–ns

t23

Data hold after WR

4 + tF

–

2 TCL - 8.5 + tF

–ns

t25

ALE rising edge after RD, WR

15 + tF

–

2 TCL -10 + tF

–ns

t27

Address/Unlatched CS hold

after RD, WR

10 + tF

–

2 TCL -15 + tF

–ns

t38

ALE falling edge to Latched CS

-4 - tA

10 - tA

-4 - tA

10 - tA

t39

Latched CS low to Valid Data In

–

18.5 + tC +

2tA

–

3 TCL - 19

+ tC + 2tA

t40

Latched CS hold after RD, WR

27 + tF

–

3 TCL - 10.5 + tF

–ns

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