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ST10F280 数据表(PDF) 161 Page - STMicroelectronics

部件名 ST10F280
功能描述  16-BIT MCU WITH MAC UNIT, 512K BYTE FLASH MEMORY AND 18K BYTE RAM
PDF  186 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST10F280 数据表(HTML) 161 Page - STMicroelectronics

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The mechanism used to generate the CPU clock is selected during reset by the logic levels on pins
P0.15-13 (P0H.7-5).
20.4.3 - Clock Generation Modes
The Table 40 associates the combinations of these three bit with the respective clock generation mode.
Notes: 1. The external clock input range refers to a CPU clock range of 1...40MHz.
2. The maximum depends on the duty cycle of the external clock signal.
3. The maximum input frequency is 25MHz when using an external crystal with the internal oscillator; providing that internal serial
resistance of the crystal is less than 40
Ω. However, higher frequencies can be applied with an external clock source on pin XTAL1,
but in this case, the input clock signal must reach the defined levels VIL and VIH2..
4. The PLL free-running frequency is from 2 to 10MHz.
Figure 77 : Generation Mechanisms for the CPU Clock
Table 40 : CPU Frequency Generation
P0H.7 P0H.6 P0H.5 CPU Frequency fCPU = fXTAL x F External Clock Input Range1
Notes
11
1
fXTAL x 4
2.5 to 10MHz
Default configuration
11
0
fXTAL x 3
3.33 to 13.33MHz
10
1
fXTAL x 2
5 to 20MHz
10
0
fXTAL x 5
2 to 8MHz
01
1
fXTAL x 1
1 to 40MHz
Direct drive 2 4
01
0
fXTAL x 10
1 to 4MHz
00
1
fXTAL x 0.5
2 to 80MHz
CPU clock via prescaler3
00
0
fXTAL x 2.5
4 to 16MHz
TCL TCL
fCPU
fXTAL
fCPU
fXTAL
Phase locked loop operation
Direct Clock Drive
TCL
TCL
fCPU
fXTAL
Prescaler Operation
TCL TCL



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