ST10F280 datasheet(159/186 Pages) STMICROELECTRONICS

159 / 186 page

ST10F280

159/186

20.3.2 - Conversion Timing Control

When

conversion

started,

first

the

capacitances of the converter are loaded via the

respective analog input pin to the current analog

input voltage. The time to load the capacitances is

referred to as the sample time ts. Next the

sampled voltage is converted to a digital value in

10 successive steps, which correspond to the

10-bit resolution of the ADC. The next 4 steps are

used for equalizing internal levels (and are keep

for exact timing matching with the 10-bit A/D

converter module implemented in ST10F168).

The current that has to be drawn from the sources

for sampling and changing charges depends on

the time that each respective step takes, because

the capacitors must reach their final voltage level

within the given time, at least with a certain

approximation. The maximum current, however,

that a source can deliver, depends on its internal

resistance.

The sample time tS (= 2 tSC) and the conversion

time tC (= 14 tCC + 2 tSC + 4 TCL) can be

programmed relatively to the ST10F280 CPU

clock. This allows adjusting the A/D converter of

the ST10F280 to the properties of the system:

Fast

Conversion

can

achieved

programming

the

respective

times

their

absolute possible minimum. This is preferable for

scanning high frequency signals. The internal

resistance of analog source and analog supply

must be sufficiently low, however.

High Internal Resistance can be achieved by

programming the respective times to a higher

value, or the possible maximum. This is preferable

when using analog sources and supply with a high

internal resistance in order to keep the current as

low as possible. However, the conversion rate in

this case may be considerably lower.

The conversion times are programmed via the

upper four bit of register ADCON. Bit field ADCTC

(conversion

time

control)

selects

the

basic

conversion clock tCC, used for the 14 steps of

converting. The sample time tS is a multiple of this

conversion time and is selected by bit field

ADSTC (sample time control). The table below

lists the possible combinations. The timings refer

to the unit TCL, where fCPU = 1/2 TCL.

A complete conversion will take 14 tCC + 2 tSC + 4 TCL (fastest convertion rate = 4.85µs at 40MHz). This

time includes the conversion itself, the sample time and the time required to transfer the digital value to

the result register.

Table 39 : ADC Sampling and Conversion Timing

ADCTC

Conversion Clock tCC

ADSTC

Sample Clock tSC

TCL = 1/2 x fXTAL

At fCPU = 40MHz

tSC =

At fCPU = 40MHz

and ADCTC = 00

TCL x 24

0.3

µs00

tCC

0.3

µs

Reserved, do not use

Reserved

tCC x 2

0.6

µs

TCL x 96

1.2

µs10

tCC x 4

1.2

µs

TCL x 48

0.6

µs11

tCC x 8

2.4

µs

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