ST10F280 datasheet(157/186 Pages) STMICROELECTRONICS

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ST10F280

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5. This specification is only valid during Reset, or during Hold-mode or Adapt-mode. Port 6 pins are only affected if they are used for

CS output and if their open drain function is not enabled.

6. The maximum current may be drawn while the respective signal line remains inactive.

7. The minimum current must be drawn in order to drive the respective signal line active.

8. The power supply current is a function of the operating frequency. This dependency is illustrated in the Figure 74. These

parameters are tested at VDDmax and 40MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. The chip is

configured with a demultiplexed 16-bit bus, direct clock drive, 5 chip select lines and 2 segment address lines, EA pin is low during

reset. After reset, PORT 0 is driven with the value ‘00CCh’ that produces infinite execution of NOP instruction with 15 wait-state, R/

W delay, memory tristate wait state, normal ALE. Peripherals are not activated.

9. Idle mode supply current is a function of the operating frequency. This dependency is illustrated in the Figure 74. These

parameters are tested at VDDmax and 40MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH.

10. This parameter value includes leakage currents. With all inputs (including pins configured as inputs) at 0 V to 0.1V or at

VDD – 0.1V to VDD, VREF = 0V, all outputs (including pins configured as outputs) disconnected.

Figure 74 : Supply / Idle Current as a Function of Operating Frequency

fCPU [MHz]

300

ICCtyp

IIDmax

ICCmax

IIDtyp

70mA

162mA

ST10F280 数据表(PDF) 157 Page - STMicroelectronics