ST10F280 datasheet(162/186 Pages) STMICROELECTRONICS

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ST10F280

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20.4.4 - Prescaler Operation

When pins P0.15-13 (P0H.7-5) equal ’001’ during

reset, the CPU clock is derived from the internal

oscillator (input clock signal) by a 2:1 prescaler.

The frequency of fCPU is half the frequency of

fXTAL and the high and low time of fCPU (i.e. the

duration of an individual TCL) is defined by the

period of the input clock fXTAL.

The timings listed in the AC Characteristics that

refer to TCL therefore can be calculated using the

period of fXTAL for any TCL.

Note that if the bit OWDDIS in SYSCON register

is cleared, the PLL runs on its free-running

frequency and delivers the clock signal for the

Oscillator Watchdog. If bit OWDDIS is set, then

the PLL is switched off.

20.4.5 - Direct Drive

When pins P0.15-13 (P0H.7-5) equal ’011’ during

reset the on-chip phase locked loop is disabled

and the CPU clock is directly driven from the

internal oscillator with the input clock signal.

The

frequency

fCPU directly follows the

frequency of fXTAL so the high and low time of fCPU

(i.e. the duration of an individual TCL) is defined

by the duty cycle of the input clock fXTAL.

Therefor, the timings given in this chapter refer to

the minimum TCL. This minimum value can be

calculated by the following formula:

For two consecutive TCLs, the deviation caused

by the duty cycle of fXTAL is compensated, so the

duration of 2 TCL is always 1/fXTAL.

The minimum value TCLmin has to be used only

once for timings that require an odd number of

TCLs (1,3,...). Timings that require an even

number of TCLs (2,4,...) may use the formula:

Note:

The address float timings in Multiplexed

bus mode (t11 and t45) use the maximum

duration of TCL (TCLmax = 1/fXTAL x

DCmax) instead of TCLmin.

If the bit OWDDIS in SYSCON register is

cleared, the PLL runs on its free-running

frequency and delivers the clock signal for

the Oscillator Watchdog. If bit OWDDIS is

set, then the PLL is switched off.

20.4.6 - Oscillator Watchdog (OWD)

An on-chip watchdog oscillator is implemented in

the ST10F280. This feature is used for safety

operation with external crystal oscillator (using

direct drive mode with or without prescaler). This

watchdog oscillator operates as following :

The

reset default configuration enables the

watchdog oscillator. It can be disabled by setting

the OWDDIS (bit 4) of SYSCON register.

When the OWD is enabled, the PLL runs at its

free-running frequency, and it increments the

watchdog

counter.

The

PLL

free-running

frequency is from 2 to 10MHz. On each transition

of external clock, the watchdog counter is cleared.

If an external clock failure occurs, then the

watchdog counter overflows (after 16 PLL clock

cycles).

The CPU clock signal will be switched to the PLL

free-running clock signal, and the oscillator

watchdog Interrupt Request (XP3INT) is flagged.

The CPU clock will not switch back to the external

clock even if a valid external clock exits on XTAL1

pin. Only a hardware reset can switch the CPU

clock source back to direct clock input.

When the OWD is disabled, the CPU clock is

always external oscillator clock and the PLL is

switched off to decrease consumption supply

current.

20.4.7 - Phase Locked Loop

For all other combinations of pins P0.15-13

(P0H.7-5) during reset the on-chip phase locked

loop is enabled and it provides the CPU clock (see

Table 40). The PLL multiplies the input frequency

by the factor F which is selected via the

combination of pins P0.15-13 (fCPU = fXTAL x F).

With every F’th transition of fXTAL the PLL circuit

synchronizes the CPU clock to the input clock.

This synchronization is done smoothly, so the

CPU clock frequency does not change abruptly.

Due to this adaptation to the input clock the

frequency of fCPU is constantly adjusted so it is

locked to fXTAL. The slight variation causes a jitter

of fCPU which also effects the duration of

individual TCLs.

The timings listed in the AC Characteristics that

refer to TCLs therefore must be calculated using

the minimum TCL that is possible under the

respective circumstances.

TCL

min

⁄

XT ALlx l

min

duty cycle

2T CL

1 f

XT AL

⁄

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