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ST10F280 数据表(PDF) 177 Page - STMicroelectronics

部件名 ST10F280
功能描述  16-BIT MCU WITH MAC UNIT, 512K BYTE FLASH MEMORY AND 18K BYTE RAM
PDF  186 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST10F280 数据表(HTML) 177 Page - STMicroelectronics

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20.4.12 - CLKOUT and READY
VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF
Notes: 1. These timings are given for test purposes only, in order to assure recognition at a specific clock edge.
2. Demultiplexed bus is the worst case. For multiplexed bus 2 TCL are to be added to the maximum values. This adds even more
time for deactivating READY.
The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle.
Table 43 : CLKOUT and READY Characteristics
Symbol
Parameter
Maximum CPU Clock
= 40MHz
Variable CPU Clock
1/2 TCL = 1 to 40MHz
Minimum
Maximum
Minimum
Maximum
t29
CC
CLKOUT cycle time
25
25
2 TCL
2TCL
ns
t30
CC
CLKOUT high time
4
–
TCL – 8.5
–
ns
t31
CC
CLKOUT low time
3
–
TCL – 9.5
–
ns
t32
CC
CLKOUT rise time
–
4
–
4
ns
t33
CC
CLKOUT fall time
–
4
–
4
ns
t34
CC
CLKOUT rising edge to
ALE falling edge
-2 + tA
8 + tA
-2 + tA
8 + tA
ns
t35
SR
Synchronous READY
setup time to CLKOUT
12.5
–
12.5
–
ns
t36
SR
Synchronous READY
hold time after CLKOUT
2–
2
–
ns
t37
SR
Asynchronous READY
low time
35
–
2 TCL + 10
–
ns
t58
SR
Asynchronous READY
setup time
1)
12.5
–
12.5
–
ns
t59
SR
Asynchronous READY
hold time
1)
2–
2
–
ns
t60
SR
Async. READY hold time after
RD, WR high (Demultiplexed
Bus)
2)
0
0 + 2tA + tC + tF
2)
0
TCL - 12.5
+ 2tA + tC + tF
2)
ns



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