ST10F280 datasheet(181/186 Pages) STMICROELECTRONICS

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ST10F280

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20.4.14 - High-Speed Synchronous Serial Interface (SSC) Timing

20.4.14.1 Master Mode

VCC = 5V ±10%, VSS = 0V, CPU clock = 40MHz, TA = -40 to +125°C, CL = 50pF

Note: 1. Timing guaranteed by design.

The formula for SSC Clock Cycle time is : t300 = 4 TCL * (<SSCBR> + 1)

Where <SSCBR> represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer.

Notes: 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn

in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b).

2. The bit timing is repeated for all bits to be transmitted or received.

Symbol

Parameter

Maximum Baud rate = 10M Baud

(<SSCBR> = 0001h)

Variable Baud rate

(<SSCBR>=0001h-FFFFh)

Unit

Minimum

Maximum

Minimum

Maximum

t300

CC SSC clock cycle time

100

8 TCL

262144 TCL

t301

CC SSC clock high time

–

t300/2 - 10

–ns

t302

CC SSC clock low time

–

t300/2 - 10

–ns

t303

CC SSC clock rise time

–

t304

CC SSC clock fall time

–

t305

CC Write data valid after shift edge

–

t306

CC Write data hold after shift edge 1

-2

–

-2

–

t307p SR Read data setup time before

latch edge, phase error

detection on (SSCPEN = 1)

37.5

–

2 TCL + 12.5

–

t308p SR Read data hold time after latch

edge, phase error detection on

(SSCPEN = 1)

–

4 TCL

–

t307

SR Read data setup time before

latch edge, phase error

detection off (SSCPEN = 0)

–

2 TCL

–

t308

SR Read data hold time after latch

edge, phase error detection off

(SSCPEN = 0)

0–

–

Figure 91 : SSC Master Timing

303

304

305

306

1st Out Bit

Last Out Bit

2nd Out Bit

300

302

301

307

2nd.In Bit

1st.In Bit

308

307

Last.In Bit

308

SCLK

MTSR

MRST

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