M32CSLASH8B datasheet(336/406 Pages) RENESAS

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Under development

M32C/8B Group

23. Flash Memory

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 319 of 385

Table 23.7

Error Types and Occurrence Conditions

NOTES:

1. The flash memory enters read array mode when the command code xxFFh is written in the second bus cycle of

these commands. At the same time, the command code written in the first bus cycle is ignored.

2. When the FMR02 bit in the FMR0 register is set to 1 (lock bit disabled), no error occurs under these conditions.

FMR0 Register

(Status Register) values

Error

Error Occurrence Condition

FMR07

(SR5)

FMR06

(SR4)

Command sequence

error

• When a command is written incorrectly

• When invalid data (data other than xxD0h or xxFFh) is

written in the second bus cycle of the lock bit program

command, block erase command, read lock bit status

command, or protect bit program command(1)

Erase error

• When the block erase command is executed to a

locked block(2)

• When the block erase command is executed to an

unlocked block, but the erase operation is not

completed successfully

Program error

• When the program command is executed to a locked

block(2)

• When the program command is executed to an

unlocked block, but the program operation is not

completed successfully

• The lock bit program command is executed, but the

program operation is not completed successfully

• The protect bit program command is executed, but the

program operation is not completed successfully

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