数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

M32C/8B 数据表(PDF) 88 Page - Renesas Technology Corp

部件名 M32C/8B
功能描述  RENESAS MCU M16C FAMILY / M32C/80 SERIES
PDF  406 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

M32C/8B 数据表(HTML) 88 Page - Renesas Technology Corp

Back Button M32C/8B Datasheet HTML 84Page - Renesas Technology Corp M32C/8B Datasheet HTML 85Page - Renesas Technology Corp M32C/8B Datasheet HTML 86Page - Renesas Technology Corp M32C/8B Datasheet HTML 87Page - Renesas Technology Corp M32C/8B Datasheet HTML 88Page - Renesas Technology Corp M32C/8B Datasheet HTML 89Page - Renesas Technology Corp M32C/8B Datasheet HTML 90Page - Renesas Technology Corp M32C/8B Datasheet HTML 91Page - Renesas Technology Corp M32C/8B Datasheet HTML 92Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 88 / 406 page
background image
Under development
M32C/8B Group
9. Clock Generation Circuits
Preliminary specification
Specifications in this manual are tentative and subject to change.
REJ09B0450-0050 Rev.0.50 Oct 31, 2008
Page 71 of 385
Figure 9.6
PLC0 Register
b7
0
b6 b5 b4
b1
b2
b3
PLL Control Register 0 (1)(2)
Symbol
PLC0
Address
0026h
Bit Symbol
Bit Name
RW
PLC00
After Reset
0001 X010b
NOTES:
1. Set the PLC0 register after the PRC0 bit in the PRCR register is set to 1 (write enable).
2. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), a write to the PLC0 register has no effect.
3. Set bits PLC02 to PLC00 while the PLC07 bit is 0. Bits PLC02 to PLC00 can be written only once.
4. Enter wait mode or stop mode after the CM17 bit is set to 0 (main clock as CPU clock source) and then the PLC07 bit to 0.
5. The frequency of PLL clock is calculated by the following equation.
b0
Function
PLL clock multiplication factor
select bits(3)(5)
PLC01
PLC02
b2 b1 b0
0 1 0: Multiply-by-4
1 0 0: Multiply-by-8
Do not set to values other than the above
(b3)
RW
RW
RW
PLC05
RW
Set to 0
(b6)
PLC07
Reference clock division rate
select bits(3)(5)
Reserved bit
b5 b4
0 0: No division
0 1: Divide-by-2
1 0: Divide-by-4
Do not set to values other than the above
0: PLL stops
1: PLL runs
Operation enable bit(4)
RW
RW
RW
Unimplemented.
Write 0. Read as undefined value.
PLC04
PLL clock frequency = Main clock frequency
×
× PLL clock multiplication factor
1
Reference clock division rate
Set by bits PLC02 to PLC00.
Set by bits PLC05 and PLC04.
8
4
e.g.) Main clock frequency: 10 MHz
Bits PLC02 to PLC00: 100b (multiply-by-8)
PLL clock frequency = 10 MHz
×
= 20 MHz
Bits PLC05 and PLC04: 10b (divide-by-4)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com