M32CSLASH8B datasheet(35/406 Pages) RENESAS

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M32C/8B Group

2. Central Processing Unit (CPU)

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 18 of 385

Central Processing Unit (CPU)

R0H

R0L

R1H

R1L

Static base register(1)

Frame base register(1)

Carry flag

Debug flag

Zero flag

Sign flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved

Processor interrupt priority level

Reserved

R0L

R1L

USP

INTB

ISP

R0H

R1H

b31

b15

b23

FLG

IPL

b15

b8 b7

SVF

SVP

VCT

b23

b15

DMD0

DMD1

DCT0

DCT1

DRC0

DRC1

DMA0

DMA1

DRA0

DRA1

DSA0

DSA1

b23

b15

Address registers(1)

User stack pointer

Interrupt stack pointer

Interrupt table register

Program counter

Flag register

General registers

High-speed interrupt registers

DMAC-associated registers

Flag save register

PC save register

Vector register

DMA mode registers

DMA transfer count registers

DMA transfer count reload registers

DMA memory address registers

DMA memory address reload registers

DMA SFR address registers

NOTE:

1. These registers comprise a register bank.

There are two sets of register banks (register bank 0 and register bank 1).

Data registers(1)

Figure 2.1 shows the CPU registers.

The register bank is comprised of eight registers (R0, R1, R2, R3, A0, A1, SB, and FB) out of 28 CPU registers. There

are two sets of register banks.

Figure 2.1

CPU Register

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