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M32C/8B Group

7. Processor Mode

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 40 of 385

Processor Mode

7.1

Processor Mode

Single-chip mode, memory expansion mode, microprocessor mode, or boot mode can be selected as the processor

mode. Table 7.1 lists the features of the processor mode.

Table 7.1

Processor Mode Features

NOTES:

1. Refer to 8. Bus for details.

2. Refer to 25. Flash Memory for details.

7.2

Setting of Processor Mode

The CNVSS pin, EPM(P5_5) pin, and bits PM01 and PM00 in the PM0 register determine which processor mode

to select. Table 7.2 lists processor mode after hardware reset. Table 7.3 lists the processor mode selected by bits

PM01 and PM00.

Table 7.2

Processor Mode after Hardware Reset

NOTE:

1. P5_5 functions as the HOLD pin after reset.

Table 7.3

PM01 and PM00 Bits Setting and Processor Mode

Rewriting bits PM01 and PM00 in the PM0 register places the MCU in the corresponding processor mode

regardless of the CNVSS input level. When using memory expansion mode or microprocessor mode, first set bits

PM02, PM05 and PM04, and PM07 in the PM0 register, and also set bits PM11 and PM10, PM15 and PM14 in the

PM1 register. Then, set bits PM01 and PM00.

Do not enter microprocessor mode while the CPU is executing the program in the internal ROM.

Do not enter single-chip mode from microprocessor mode while the CPU is executing the program in an external

space.

The internal ROM cannot be accessed regardless of the PM01 and PM00 bits setting if the MCU starts up in

microprocessor mode after reset.

Figures 7.1 and 7.2 show the PM0 register and PM1 register. Figure 7.3 shows a memory map in each processor

mode.

Processor Mode

Accessible Space

Pins assigned to I/O Port

Single-chip mode

SFR, internal RAM, internal ROM (user

ROM area)

Used as I/O ports or I/O pins for peripheral

functions

Memory expansion mode(1) SFR, internal RAM, internal ROM (user

ROM area), external space

P0 to P5 become bus control pins

Microprocessor mode(1)

SFR, internal RAM, external space

P0 to P5 become bus control pins

Boot mode(2)

SFR, internal RAM, internal ROM (boot

ROM area)

Used as I/O ports or I/O pins for peripheral

functions

Input to mode entry pins

Chip Type

Processor Mode

CNVSS pin

EPM(P5_5)

H or L

Flash memory version

Single-chip mode

HH(1)

Flash memory version,

ROMless version

Microprocessor mode

Flash memory version

Boot mode

Bits PM01 and PM00

Processor Mode

00b

Single-chip mode

01b

Memory expansion mode

11b

Microprocessor mode

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