M32CSLASH8B datasheet(84/406 Pages) RENESAS

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M32C/8B Group

9. Clock Generation Circuits

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 67 of 385

Figure 9.2

CM0 Register

b7 b6 b5 b4

System Clock Control Register 0(1)

Symbol

CM0

Address

0006h

Bit Symbol

Bit Name

CM00

After Reset

0000 1000b

NOTES:

1. Set the CM0 register after the PRC0 bit in the PRCR register is set to 1 (write enable).

2. The BCLK, ALE, or "L" signal is output from the P5_3 in memory expansion mode or microprocessor mode. Port P5_3 does not

function as an I/O port.

3. fC32 does not stop running.

4. To set the CM04 bit to 1, set bits PD8_7 and PD8_6 in the PD8 register to 00b (ports P8_6 and P8_7 in input mode) and the

PU25 bit in the PUR2 register to 0 (not pulled up).

5. The CM05 bit stops the main clock oscillation when entering low-power consumption mode or on-chip oscillator low-power

consumption mode. The CM05 bit cannot be used to determine whether the main clock stops or not. To stop the main clock

oscillation, set the PLC07 bit in the PLC0 register to 0 and the CM05 bit to 1 after setting the CM07 bit to 1 or setting the CM21

bit in the CM2 register to 1 (on-chip oscillator clock).

When the CM05 bit is set to 1, the XOUT pin outputs "H". Since an on-chip feedback resistor remains ON, the XIN pin is pulled

up to the XOUT pin via the feedback resistor.

6. When the CM05 bit is set to 1, bits MCD4 to MCD0 in the MCD register become 01000b (divide-by-8 mode). In on-chip

oscillator mode, bits MCD4 to MCD0 do not become 01000b even if the CM05 bit is set to 1.

7. Once the CM06 bit is set to 1, it cannot be set to 0 by a program.

8. Change the CM07 bit setting from 0 to 1, after the CM04 bit is set to 1 and the sub clock oscillation stabilizes.

Change the CM07 bit setting from 1 to 0, after the CM05 bit is set to 0 and the main clock oscillation stabilizes.

Do not change the CM07 bit simultaneously with the CM04 or CM05 bit.

9. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), a write to bits CM02, CM05, and CM07 has no effect.

10. When stop mode is entered, the CM03 bit becomes 1.

Function

b1 b0

0 0: I/O port P5_3(2)

0 1: Outputs fC

1 0: Outputs f8

1 1: Outputs f32

Clock output function select bits(2)

CM01

CM02

Peripheral function clock stop

in wait mode bit(9)

0: Peripheral clocks do not stop in wait mode

1: Peripheral clocks stop in wait mode(3)

CM03

XCIN-XCOUT drive capability

select bit(10)

0: Low

1: High

CM04

Port XC switch bit

0: I/O port function

1: XCIN-XCOUT oscillation function(4)

CM05

Main clock (XIN-XOUT)

stop bit(5, 9)

0: Main clock oscillates

1: Main clock stops(6)

CM06

Watchdog timer

function select bit

CPU clock select bit 0(8, 9)

0: Watchdog timer interrupt

1: Reset(7)

CM07

0: Clock selected by the CM21 bit divided by

the MCD register

1: Sub clock

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