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M32C/8B 数据表(PDF) 77 Page - Renesas Technology Corp |
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M32C/8B 数据表(HTML) 77 Page - Renesas Technology Corp |
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77 / 406 page  Under development M32C/8B Group 8. Bus Preliminary specification Specifications in this manual are tentative and subject to change. REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 60 of 385 8.2.8 External Bus States when Accessing Internal Space Table 8.9 lists external bus states when the internal space is accessed. Table 8.9 External Bus States when Accessing Internal Space 8.2.9 BCLK Output The bus clock can be output from the BCLK pin in memory expansion mode and microprocessor mode. To output the bus clock, set the PM07 bit in the PM0 register to 0 (BCLK output) and bits CM01 and CM00 in the CM0 register to 00b (I/O port P5_3). No BCLK is output in single-chip mode. Refer to 9. Clock Generation Circuits for details. Item State when Accessing SFR, Internal ROM, and Internal RAM A0 to A22, A23 Hold the last accessed address in the external space D0 to D15 High-impedance RD, WR, WRL, WRH Outputs “H” BHE Holds the output level at the time when the MCU accessed the external space or SFR area for the last time CS Outputs “H” ALE Outputs ALE signal |
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