M32CSLASH8B datasheet(74/406 Pages) RENESAS

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Under development

M32C/8B Group

8. Bus

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 57 of 385

8.2.4.1

Bus Cycle with Recovery Cycle Inserted

The EWCRi6 bit in the EWCRi register (i = 0 to 3) determines whether the recovery cycle is inserted or not.

Address output or data output is held during the recovery cycle (only when using the separate bus). Devices,

which require longer address hold time or data hold time, are connectable.

Figure 8.9

Recovery Cycle

- Recovery cycle when separate bus is selected (

bus cycle is 1 φ + 2 φ)

BCLK

Address

CSi

Read data

Write data

WR, WRL, WRH

- Recovery cycle when multiplexed bus is selected (

bus cycle is 2 φ + 3 φ)

A: address

LA: Latch address

RD: Read data

WD: Write data

i = 0 to 3

NOTE:

1. When the MCU accesses the same CS area consecutively, the CSi pin keeps outputting "L".

(Note 1)

Recovery cycle

Address is held

BCLK

CSi

Read data

Write data

WR (WRL)

ALE

(Note 1)

Recovery cycle

Data is held

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