M32CSLASH8B datasheet(63/406 Pages) RENESAS

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Under development

M32C/8B Group

8. Bus

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 46 of 385

Table 8.3

Processor Mode and Pin Function

NOTES:

1. Do not set bits PM05 and PM04 in the PM0 register to 11b (access all CS areas using multiplexed bus) in

microprocessor mode since the MCU starts up with the separate bus after reset. When bits PM05 and PM04

are set to 11b in memory expansion mode, the accessible space is 64-Kbyte per each chip-select output.

2. These pins are used as address bus when selecting separate bus.

3. Bits PM15 and PM14 in the PM1 register determine which pin is used to output the ALE signal.

4. The PM02 bit in the PM0 register selects either combination, “RD, WRL, WRH” or “RD, BHE, WR”.

5. P5_6 outputs undefined value when bits PM15 and PM14 are set to 00b (no ALE). In this case, it cannot be

used as an I/O port.

6. Bits PM11 and PM10 in the PM1 register determine whether these pins are used as chip-select outputs or

address bus.

7. Use bits CM01 and CM00 in the CM0 register, bits PM15 and PM14 in the PM1 register, and the PM07 bit in

the PM0 register to select among CLKOUT, BCLK, and ALE function.

Processor

Mode

Single-chip

Mode

Memory Expansion Mode/Microprocessor Mode

Memory Expansion Mode

PM05 and

PM04 bits

setting(1)

00b

(Multiplexed bus not used)

01b (Access CS2 area

using multiplexed bus)

10b (Access CS1 area

using multiplexed bus)

11b

(Access all CS areas using

multiplexed bus)

Data bus width

Access all

external

spaces with

8-bit data

bus

Access any

external

spaces with

16-bit data

bus

Access all

external

spaces with

8-bit data

bus

Access any

external

spaces with

16-bit data

bus

Access all

external

spaces with

8-bit data

bus

Access any

external

spaces with

16-bit data

bus

P0_0 to P0_7

I/O port

Data bus (D0 to D7)

I/O port

P1_0 to P1_7

I/O port

Data bus

(D8 to D15)

I/O port

Data bus

(D8 to D15)

P2_0 to P2_7

Address bus (A0 to A7)

Address bus/data bus (A0/D0 to A7/D7)(2)

P3_0 to P3_7

Address bus (A8 to A15)

Address bus/

data bus

(A8/D8 to

A15/D15)(2)

Address bus

(A8 to A15)

Address bus/

data bus

(A8/D8 to

A15/D15)(2)

P4_0 to P4_3

Address Bus (A16 to A19)

I/O port

P4_4 to P4_6

CS or address bus (A20 to A22) (Refer to 8.2 Bus Control for details)(6)

P4_7

CS or address bus (A23) (Refer to 8.2 Bus Control for details)(6)

P5_0 to P5_2

RD, WRL, WRH outputs or RD, BHE, WR outputs

(Refer to 8.2 Bus Control for details)(4)

P5_3

I/O port/

CLKOUT

CLKOUT/BCLK/ALE(7)

P5_4

I/O port

HLDA/ALE(3)

P5_5

HOLD

P5_6

ALE(3)(5)

P5_7

RDY

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