M32CSLASH8B datasheet(83/406 Pages) RENESAS

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Under development

M32C/8B Group

9. Clock Generation Circuits

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 66 of 385

Figure 9.1

Clock Generation Circuit

WAIT instruction

R Q

PLL frequency

synthesizer

On-chip

oscillator

Enable oscillation

CM17 CM21

Divider

(divide-by-m)

CM04

XCIN

XCOUT

Sub clock oscillation circuit

XIN

XOUT

Main clock oscillation circuit

1/8

1/4

fROC

1/2n

fAD

f32

f2n(1)

PM27 and PM26

CST

Peripheral function

clock source: fPFC

fXIND

fROC

1/32

fC32

CPSR=1

CPU clock

(bus clock)

fCPU

CM05

PM26

fXIND

CM07

Stop mode

PM26

PM27

PM22

CM21

Stop mode

CM02

PM21

Clock stop signal

in wait mode

Clock stop signal

in wait mode

Stop mode

Software reset

Watchdog timer reset

Reset the

divider (divide-

by-8 mode)

Main clock

Clock stop signal in wait mode

CM05

CM21

CM10

Clock stop signal

in wait mode

Stop mode

RESET

Voltage monitor

interrupt signal

NMI

S Q

Logic 1 write signal

to CM10 bit

Reset the divider

fPLL

VDEN: bit in the LVDC register

VC27: bit in the VCR2 register

CM02, CM04, CM05, and CM07: bits in the CM0 register

CM10 and CM17: bits in the CM1 register

CM21: bit in the CM2 regsiter

PM21, PM22, PM26, and PM27: bits in the PM2 register

CST: bit in the TCSPR register

CPSR: bit in the CPSRF register

NOTES:

1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).

2. Bits MCD4 to MCD0 in the MCD register select the dividing ratio (divide-by-m mode: m = 1, 2, 3, 4, 6, 8, 10, 12, 14, 16).

Watchdog timer

interrupt request signal

Oscillation stop detection

interrupt request

(non-maskable interrupt requst)

CM21

Voltage monitor

interrupt signal

Oscillation stop detection circuit

Clock edge detect/

charge and discharge

circuit control

Main clock

Charge and

discharge circuit

Oscillation stop detection

interrupt request

generation circuit

MCD register(2)

VDEN

Request signal used to wake-up

from wait mode/stop mode

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