M32CSLASH8B datasheet(59/406 Pages) RENESAS

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Under development

M32C/8B Group

7. Processor Mode

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 42 of 385

Figure 7.2

PM1 Register

b7 b6 b5 b4

Processor Mode Register 1(1)

Symbol

PM1

Address

0005h

Bit Symbol

Bit Name

PM10

Function

External space mode bits(2)

PM11

b1 b0

0 0: Mode 0 (A20 to A23 for P4_4 to P4_7)

0 1: Mode 1 (A20 for P4_4,

CS2 to CS0 for P4_5 to P4_7)

1 0: Mode 2 (A20 and A21 for P4_4 and P4_5,

CS1 and CS0 for P4_6 and P4_7)

1 1: Mode 3 (CS3 to CS0 for P4_4 to P4_7)

PM12

Internal memory wait bit

0: No wait state

1: 1 wait state

PM13

SFR area wait bit

PM14

PM15

Reserved bits

Set to 0

ALE pin select bits(2)

b5 b4

0 0: No ALE

0 1: P5_3(3)

1 0: P5_6

1 1: P5_4

−

(b7-b6)

0 0

0: 1 wait state

1: 2 wait states

After Reset

00h

NOTES:

1. Set the PM1 register after the PRC1 bit in the PRCR register is set to 1 (write enable).

2. The PM11 and PM10 bits settings are enabled in memory expansion mode and microprocessor mode. Set bits PM01 and

PM00 after setting bits PM15 and PM14, and bits PM11 and PM10.

3. To output ALE signal from P5_3, set bits PM15 and PM14 to 01b, and bits CM01 and CM00 in the CM0 register to 00b (I/O port

P5_3).

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