M32CSLASH8B datasheet(96/406 Pages) RENESAS

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M32C/8B Group

9. Clock Generation Circuits

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 79 of 385

9.1.4

PLL Clock

The PLL frequency synthesizer generates the PLL clock by multiplying the main clock. The PLL clock can be

used as the clock source for the CPU clock and peripheral function clocks. Figure 9.13 shows the block diagram

of PLL frequency synthesizer.

Figure 9.13

PLL Frequency Synthesizer Block Diagram

The PLL clock frequency is calculated by the following equation. Table 9.3 lists the PLL clock frequency

settings examples.

Table 9.3

The PLL Clock Frequency Settings Examples

The PLL frequency synthesizer is stopped after reset. When the PLC07 bit in the PLC0 register is set to 1 (PLL

runs), the PLL frequency synthesizer starts operating. Waiting time, tsu(PLL), is required before the PLL clock

is stabilized.

Prior to entering wait mode or stop mode, set the CM17 bit in the CM1 register to 0 (main clock as CPU clock

source), and then set the PLC07 bit to 0 (PLL stops).

Figure 9.14 shows the procedure to use the PLL clock as the CPU clock source.

Main Clock

(fXIN)

PLC0 Register

PLL Clock

(fPLL)

Bits PLC05 and PLC04

Bits PLC02 to PLC00

5 MHz

01b (Divide-by-2)

100b (Multiply-by-8)

fPLL = fXIN × 1/2 × 8 = 20 MHz

10 MHz

10b (Divide-by-4)

100b (Multiply-by-8)

fPLL = fXIN × 1/4 × 8 = 20 MHz

8 MHz

01b (Divide-by-2)

100b (Multiply-by-8)

fPLL = fXIN × 1/2 × 8 = 32 MHz

16 MHz

10b (Divide-by-4)

100b (Multiply-by-8)

fPLL = fXIN × 1/4 × 8 = 32 MHz

Loop filter

NOTES:

1. The frequency after the main clock is divided by the reference clock divider is set to be from 2 MHz to 4 MHz.

2. Set the PLL clock frequency as follows: 10 MHz

≤ the PLL clock frequency ≤ 32 MHz

VCO clock divider

Reference clock

divider

Phase

comparator

PLL clock (fPLL)(2)

VCO clock (fVCO)

Voltage

controlled

oscillator

(VCO)

Main clock

VCO clock divider

(Note 1)

PLL clock frequency = Main clock frequency

Division rate of

VCO clock divider A

Division rate of

the reference clock divider

Set by bits PLC02 to PLC00

Set by bits PLC05 and PLC04

Division rate of

VCO clock divider B

PLC05, PLC04, and PLC02 to PLC00: Bits in the PLC0 register

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