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M32C/8B 数据表(PDF) 72 Page - Renesas Technology Corp |
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M32C/8B 数据表(HTML) 72 Page - Renesas Technology Corp |
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72 / 406 page ![]() Under development M32C/8B Group 8. Bus Preliminary specification Specifications in this manual are tentative and subject to change. REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 55 of 385 Figure 8.7 Bus Cycles when Multiplexed Bus is Selected (1/2) 1 bus cycle = 6 φ 1 bus cycle = 7 φ RD RD • Bus cycle 2 φ + 2 φ BCLK CSi Read data Write data RD • Bus cycle 2 φ + 3 φ • Bus cycle 2 φ + 5 φ ALE BCLK CSi Read data Write data RD ALE BCLK CSi Read data Write data RD ALE (Note 1) (Note 1) (Note 1) • Bus cycle 3 φ + 3 φ BCLK CSi Read data Write data RD ALE (Note 1) LA LA 1 bus cycle = 4 φ WD LA LA WD LA LA i=0 to 3 LA LA RD WD RD WD WR (WRL) WR (WRL) WR (WRL) WR (WRL) 1 bus cycle = 5 φ LA: Latch address RD: Read data WD: Write data NOTE: 1. When the MCU accesses the same CS area consecutively, the CSi pin keeps outputting "L". |
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