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M32C/8B 数据表(PDF) 51 Page - Renesas Technology Corp |
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M32C/8B 数据表(HTML) 51 Page - Renesas Technology Corp |
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51 / 406 page ![]() Under development M32C/8B Group 5. Reset Preliminary specification Specifications in this manual are tentative and subject to change. REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 34 of 385 Figure 5.2 Reset Sequence 300 to 308 BCLK cycles FFFFFFh Microprocessor mode BYTE = "H" Content of reset vector NOTE: 1. Address data is not output from pins in single-chip mode. FFFFFCh FFFFFDh FFFFFEh FFFFFCh FFFFFEh Content of reset vector Address(1) Content of reset vector Address A23 RD WR Address FFFFFEh FFFFFCh Microprocessor mode BYTE = "L" Single-chip mode A23 RD WR VCC1, VCC2 XIN RESET BCLK 20 or more clock cycles are required Td(P-R) ms or more is required “H” “L” “H” “L” “H” “L” “H” “L” “H” “L” “H” “L” |
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