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M32C/8B 数据表(PDF) 66 Page - Renesas Technology Corp |
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M32C/8B 数据表(HTML) 66 Page - Renesas Technology Corp |
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66 / 406 page  Under development M32C/8B Group 8. Bus Preliminary specification Specifications in this manual are tentative and subject to change. REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 49 of 385 8.2.3 Read/Write Output Signals When using a 16-bit data bus, the PM02 bit in the PM0 register selects either a combination of the “RD, WR, and BHE” outputs or the “RD, WRL, and WRH” outputs to determine the read/write output signals. When bits DS3 to DS0 in the DS register are set to 0 (8-bit external data bus width), set the PM02 bit to 0 (RD/WR/BHE). When any of bits DS3 to DS0 is set to 1 (16-bit external data bus width) to access an 8-bit space, the combination of “RD, WR, and BHE” is automatically selected regardless of the PM02 bit setting. Table 8.4 lists RD, WRL, and WRH outputs. Table 8.5 list RD, WR, and BHE outputs. The RD, WR, and BHE outputs are selected for the read/write output signals after reset. When changing to “RD, WRL, and WRH” outputs, set the PM02 bit first to write data to an external memory. Table 8.4 RD, WRL, and WRH Outputs NOTE: 1. These become WR output. Table 8.5 RD, WR, and BHE Outputs Data Bus Width RD WRL WRH A0 CPU Processing on External Space 16 bits L H H Not used Read data H L H Not used Write 1-byte data to even address H H L Not used Write 1-byte data to odd address H L L Not used Write data to both even and odd addresses 8 bits H L(1) Not used H/L Write 1-byte data LH(1) Not used H/L Read 1-byte data Data Bus Width RD WR BHE A0 CPU Processing on External Space 16 bits H L L H Write 1-byte data to odd address L H L H Read 1-byte data from odd address H L H L Write 1-byte data to even address L H H L Read 1-byte data from even address H L L L Write data to both even and odd addresses L H L L Read data from both even and odd addresses 8 bits H L Not used H/L Write 1-byte data L H Not used H/L Read 1-byte data |
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