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M32C/8B 数据表(PDF) 97 Page - Renesas Technology Corp |
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M32C/8B 数据表(HTML) 97 Page - Renesas Technology Corp |
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97 / 406 page  Under development M32C/8B Group 9. Clock Generation Circuits Preliminary specification Specifications in this manual are tentative and subject to change. REJ09B0450-0050 Rev.0.50 Oct 31, 2008 Page 80 of 385 Figure 9.14 Procedure to Use PLL Clock as CPU Clock Source Start End PLC0 register: bits PLC05 and PLC04 PLC0 register: bits PLC02 to PLC00 PRCR register: PRC0 bit = 1 PLC0 register: PLC07 bit = 1 CM1 register : CM17 bit = 1 PRC0 bit = 0 Wait for tsu(PLL) Enable writing to registers associated with clocks CM2 register: CM21 bit = 0 CM0 register: CM07 bit = 0 Select the main clock as the CPU clock source (Set after a main clock oscillation stabilizes) Select the reference clock division rate for the PLL clock Select the PLL clock multiplication factor PLL runs Select the PLL clock as the clock source for the CPU clock and peripheral function clock Disable writing to registers associated with clocks Wait for PLL frequency synthesizer to stabilize |
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