M32CSLASH8B datasheet(101/406 Pages) RENESAS

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M32C/8B Group

9. Clock Generation Circuits

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 84 of 385

9.5.1.1

Main Clock Mode

The main clock divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 is used as the source for the CPU clock.

The main clock is also used as the source for fPFC. When the sub clock is running, fC32 can be used as the

count source for timer A and timer B.

9.5.1.2

PLL Mode

The PLL clock divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 is used as the source for the CPU clock.

The PLL clock is also used as the source for fPFC. When the sub clock is running, fC32 can be used as the

count source for timer A and timer B.

9.5.1.3

Low-Speed Mode

The sub clock is used as the source for the CPU clock. The main clock, PLL clock, or on-chip oscillator clock

can be selected as the source for fPFC by setting bits CM17 and CM21 after the CPU clock is switched to the

sub clock using the CM07 bit. In low-speed mode, fC32 can be used as the count source for timer A and

timer B.

Out of CPU operating modes, only main clock mode and low-power consumption mode can be entered from

low-speed mode. Enter main clock mode first prior to entering different CPU operating modes other than the

low-power consumption mode.

9.5.1.4

Low-Power Consumption Mode

The MCU enters low-power consumption mode when the main clock stops in low-speed mode. The sub clock is

used as the source for the CPU clock. The on-chip oscillator clock can be selected as the source for fPFC by

setting the CM21 bit after entering low-power consumption mode. fC32 can be used as the count source for

timer A and timer B. When low-power consumption mode is entered, bits MCD4 to MCD0 in the MCD register

become 01000b (divide-by-8 mode). Therefore, when next time the CPU clock source is switched to the main

clock, the CPU clock is the main clock divided by eight. However, bits MCD4 to MCD0 do not become 01000b

if the main clock is stopped by setting the CM05 bit to 1 while the on-ship oscillator clock is selected as the

source for fPFC in low-speed mode. In this case, set bits MCD4 to MCD0 to 01000b by a program and then

switch the CPU clock source to the main clock.Figure 9.16 shows the procedure to enter low-power

consumption mode from main clock mode.

9.5.1.5

On-Chip Oscillator Mode

The on-chip oscillator clock divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 is used as the source for

the CPU clock. The on-chip oscillator clock is also used as the source for fPFC. When the sub clock is running,

fC32 can be used as the count source for timer A and timer B.

9.5.1.6

On-Chip Oscillator Low-Power Consumption Mode

The MCU enters on-chip oscillator low-power consumption mode when the main clock stops in on-chip

oscillator mode. The on-chip oscillator clock divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 is used as

the source for the CPU clock. The on-chip oscillator clock is also used as the source for fPFC. When the sub

clock is running, fC32 can be used as the count source for timer A and timer B.

9.5.1.7

Flash Memory Low-Speed Access

When the CPU clock frequency is 2 MHz or lower, power consumption can be reduced by setting the FMR40

bit in the FMR4 register to 1 (low-speed access). To configure low-speed access, set the FMR40 bit to 1 after

setting the CPU clock frequency to 2 MHz or lower. To set the CPU clock frequency to higher than 2 MHz,

change the frequency after setting the FMR40 bit to 0 (normal-speed access).

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