M32CSLASH8B datasheet(104/406 Pages) RENESAS

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Under development

M32C/8B Group

9. Clock Generation Circuits

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 87 of 385

9.5.2

Wait Mode

In wait mode, the CPU and watchdog timer stop operating. If the PM22 bit in the PM2 register is set to 1 (on-

chip oscillator clock as watchdog timer count source), the watchdog timer continues operating. Since the main

clock, sub clock, and on-chip oscillator clock continue running, peripheral functions using these clocks as their

clock source also continue to operate.

9.5.2.1

Peripheral Function Clock Stop Function

If the CM02 bit in the CM0 register is set to 1 (peripheral clocks stop in wait mode), fAD, f1, f8, and f32 stop in

wait mode. f2n, which uses the clock selected by the CM21 bit in the CM2 register as its clock source, also

stops in wait mode. Power consumption can be reduced by stopping these peripheral clocks. f2n, which uses the

XIN clock (fXIND) or on-chip oscillator clock as its clock source, and fC32 do not stop even in wait mode.

9.5.2.2

Entering Wait Mode

Figure 9.17 shows a procedure to enter wait mode.

M32C/8B 数据表(PDF) 104 Page - Renesas Technology Corp