M32CSLASH8B datasheet(91/406 Pages) RENESAS

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Under development

M32C/8B Group

9. Clock Generation Circuits

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 74 of 385

Figure 9.9

FMR4 Register, VRCR Register

b7 b6 b5 b4

Flash Memory Control Register 4(1)

Symbol

FMR4

Address

0059h

Bit Symbol

FMR40

After Reset

00h

Function

Flash memory low-speed access

enable bit

0: Normal-speed access

1: Low-speed access(2)

−

(b7-b1)

Reserved bits

Set to 0

NOTES:

Set the FMR4 register in 8-bit units. To set the FMR40 bit to 1, write a 1 to the FMR40 bit immediately after writing a 0 to

the bit. Do not generate an interrupt or a DMA or DMACII transfer between these two settings.

2. The FMR40 bit can be set to 1 only when the CPU clock frequency is 2 MHz or lower.

0 0

b7 b6 b5 b4

Voltage Regulator Control Register(1)

VRCR

001Fh

Bit Symbol

MRS

00h

Function

Main voltage regulator stop bit(3)

NOTES:

1. Set the VRCR register after the PRC3 bit in the PRCR register is set to 1 (write enable).

2. The MRS bit can be set to 1 when all the conditions as follows are met;

a. In low-power consumption mode

b. The FMR40 bit is 1

c. On-chip oscillator stops (the CM21 bit in the CM2 register is 0, the PM22 bit in the PM2 register is 0, and bits PM27 and

PM26 are 00b)

3. When the PLC07 bit in PLC0 register is 1 (PLL runs) or the CM05 bit in the CM0 register is 0 (Main clock oscillates), the

MRS bit becomes 0.

0 : Main voltage regulator operates

1 : Main voltage regulator stops(2)

Unimplemented.

Write 0. Read as undefined value.

−

(b7-b1)

−

Symbol

Address

After Reset

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