M32CSLASH8B datasheet(85/406 Pages) RENESAS

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M32C/8B Group

9. Clock Generation Circuits

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 68 of 385

Figure 9.3

CM1 Register

b6 b5 b4

System Clock Control Register 1(1)

Symbol

CM1

Address

0007h

Bit Symbol

Bit Name

CM10

After Reset

0010 0000b

NOTES:

1. Set the CM1 register after the PRC0 bit in the PRCR register is set to 1 (write enable).

2. When the CM10 bit is set to 1, the XOUT pin outputs "H" and the on-chip feedback resistor is disconnected. Pins XIN, XCIN,

and XCOUT are placed in high-impedance states.

3. When the CM10 bit is set to 1, bits MCD4 to MCD0 in the MCD register become 01000b (divide-by-8 mode).

Do not set the CM10 bit to 1, when the CM20 bit in the CM2 register is set to 1 (oscillation stop detect function used) or the

CM21 bit in the CM2 register is set to 1 (on-chip oscillator clock).

4. Set the CM17 bit to 1 after the PLL clock oscillation stablilizes.

5. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), writes to bits CM10 and CM17 have no effect.

If the PM22 bit in the PM2 register is set to 1 (on-chip oscillator clock as count source for watchdog timer), a write to the CM10

bit has no effect.

Function

All clock stop control bit(2, 3, 5)

−

(b4-b1)

−

(b5)

Reserved bits

0: Clock oscillates

1: All clocks stop (stop mode)

−

(b6)

Set to 0

CM17

CPU clock select bit 1(4, 5)

Set to 1

0: Main clock

1: PLL clock

Set to 0

Reserved bit

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