M32CSLASH8B datasheet(53/406 Pages) RENESAS

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Under development

M32C/8B Group

5. Reset

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 36 of 385

5.4

Internal Registers

Figure 5.3 shows CPU register states after reset. Refer to 4. Special Function Registers (SFRs) for SFR states

after reset.

Figure 5.3

CPU Register States after Reset

Data register (R0H/R0L)

Data register (R1H/R1L)

Data register (R2)

Data register (R3)

Address register (A0)

Address register (A1)

Static base register (SB)

Frame base register (FB)

R0H

R0L

R1H

R1L

00h

0000h

000000h

Contents of addresses

FFFFFEh to FFFFFCh

00h

b15

b23

b15

b8 b7

XXXXh

XXXXXXh

b23

b15

00h

XXXXh

XXXXXXh

b23

b15

General registers

UI O B S Z D C

IPL

0: 0 after reset

X: Undefined after reset

b15

User stack pointer (USP)

Interrupt stack pointer (ISP)

Interrupt table register (INTB)

Flag register (FLG)

High-speed interrupt registers

DMAC-associated registers

Flag save register (SVF)

PC save register (SVP)

Vector register (VCT)

DMA mode register (DMD0)

DMA mode register (DMD1)

DMA transfer count register (DCT0)

DMA transfer count register (DCT1)

DMA transfer count reload register (DRC0)

DMA transfer count reload register (DRC1)

DMA memory address register (DMA0)

DMA memory address register (DMA1)

DMA memory address reload register (DRA0)

DMA memory address reload register (DRA1)

DMA SFR address register (DSA0)

DMA SFR address register (DSA1)

Program counter (PC)

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