M32CSLASH8B datasheet(52/406 Pages) RENESAS

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Under development

M32C/8B Group

5. Reset

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 35 of 385

Table 5.1

Pin States while RESET Pin is Held “L”(2)

NOTES:

1. Ports P11 to P15 are provided in the 144-pin package only.

2. The availability of the pull-up resistors is undefined until the internal supply voltage stabilizes.

3. These pin states are defined after the power is turned on and the internal supply voltage stabilizes. Until then,

the pin states are undefined.

4. EPM (P5_5) must be “H” in the flash memory version.

5.2

Software Reset

When the PM03 bit in the PM0 register is set to 1 (MCU is reset), the MCU resets the CPU, SFRs, ports, and I/O

pins for peripheral functions. And then the MCU executes a program in an address indicated by the reset vector.

Set the PM03 bit to 1 while the main clock is selected as the clock source for the CPU clock and the main clock

oscillation is stable.

The software reset does not reset the following SFRs; bits PM01 and PM00 in the PM0 register, and the TCSPR

Processor mode remains unchanged since bits PM01 and PM00 are not reset.

5.3

Watchdog Timer Reset

When the CM06 bit in the CM0 register is set to 1 (reset) and the watchdog timer underflows, the MCU resets the

CPU, SFRs, ports, and I/O pins for peripheral functions. And then the MCU executes a program in an address

indicated by the reset vector.

The watchdog timer reset does not reset the following SFRs; bits PM01 and PM00 in the PM0 register, and the

TCSPR register.

Processor mode remains unchanged since bits PM01 and PM00 are not reset.

Pin Name

Single-Chip Mode

Microprocessor Mode

CNVSS = “L”

CNVSS = “H”(4)

BYTE = “L”

BYTE = “H”

Input port (high-impedance)

Data input (high-impedance)

Input port (high-impedance)

Data input (high-impedance)

Input port (high-impedance)

P2 to P4

Input port (high-impedance)

Address output (undefined)

P5_0

Input port (high-impedance)

WR signal output (“H”)(3)

P5_1

Input port (high-impedance)

BHE signal output (undefined)

P5_2

Input port (high-impedance)

RD signal output (“H”)(3)

P5_3

Input port (high-impedance)

BCLK output(3)

P5_4

Input port (high-impedance)

HLDA signal output (output level depends on an input level to

the HOLD pin)(3)

P5_5

Input port (high-impedance)

HOLD signal input (high-impedance)

P5_6

Input port (high-impedance)

“H” signal output(3)

P5_7

Input port (high-impedance)

RDY signal input (high-impedance)

P6 to P15(1)

Input port (high-impedance)

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