M32CSLASH8B datasheet(235/406 Pages) RENESAS

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Under development

M32C/8B Group

17. Serial Interfaces

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 218 of 385

Figure 17.17

i = 0 to 4

fEXT: clock input to the CLKi pin when the external clock is selected

NOTES:

1. Set bits SMD2 to SMD0 to the following: 100b (7 bits long), 101b (8 bits long), or 110b (9 bits long).

2. A bit order can be selected when 8-bit data length is selected. Set to 0 when 7-bit or 9-bit data length is selected.

3. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).

4. Whether data logic is inverted or not can be selected when 7-bit or 8-bit data length is selected. Set to 0 when 9-bit data

length is selected.

UART mode(1) select bits

Clock select bit

Stop bit length select bit

Parity select bit

Parity enable bit

TXD, RXD I/O polarity switch bit

UiBRG register count source select bits

CTS function select bit

CTS function disable bit

Data output select bit

Bit order select bit(2)

Transmit operation disabled

Receive operation disabled

UARTi transmit interrupt source select bit

Data logic select bit(4)

m = 00h to FFh

Baud rate =

16(m+1)

fj = f1, f8, f2n(3), fEXT

Pin settings in the Function Select Registers

UiMR register: bits SMD2 to SMD0

CKDIR bit

STPS bit

PRY bit

PRYE bit

IOPOL bit

UiSMR register = 00h

UiSMR2 register = 00h

UiSMR3 register = 00h

UiSMR4 register = 00h

UiBRG register = m

UiC1 register: TE bit = 0

RE bit = 0

UiIRS bit

UiRRM bit = 0

UiLCH bit

bit 7 = 0

Transmit operation starts by writing data to the UiTB register

UiC0 register: bits CLK1 and CLK0

CRS bit

CRD bit

NCH bit

CKPOL bit = 0

UFORM bit

Start

End

Receive operation starts when the start bit is detected.

Read the UiRB register when the receive operation is completed.

Transmit operation enabled

Receive operation enabled

UiC1 register: TE bit = 1

RE bit = 1

Transmit interrupt priority level select bits

Interrupt not requested

SiTIC register: bits ILVL2 to ILVL0

IR bit = 0

Receive interrupt priority level select bits

Interrupt not requested

SiRIC register: bits ILVL2 to ILVL0

IR bit = 0

Interrupt enabled

I flag = 1

Interrupt disabled

I flag = 0

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