H8SSLASH2214 datasheet(34/936 Pages) RENESAS

34 / 936 page

Rev.4.00 Sep. 18, 2008 Page xxxiv of lx

REJ09B0189-0400

Section 6 Bus Controller....................................................................................119

6.1

Overview............................................................................................................................ 119

6.1.1

Features................................................................................................................. 119

6.1.2

Block Diagram...................................................................................................... 120

6.1.3

Pin Configuration.................................................................................................. 121

6.1.4

6.2

Register Descriptions ......................................................................................................... 123

6.2.1

Bus Width Control Register (ABWCR)................................................................ 123

6.2.2

Access State Control Register (ASTCR) .............................................................. 124

6.2.3

Wait Control Registers H and L (WCRH, WCRL)............................................... 125

6.2.4

Bus Control Register H (BCRH) .......................................................................... 129

6.2.5

Bus Control Register L (BCRL) ........................................................................... 131

6.2.6

Pin Function Control Register (PFCR) ................................................................. 132

6.3

Overview of Bus Control ................................................................................................... 134

6.3.1

Area Divisions ...................................................................................................... 134

6.3.2

Bus Specifications................................................................................................. 135

6.3.3

Memory Interfaces ................................................................................................ 136

6.3.4

Interface Specifications for Each Area ................................................................. 137

6.3.5

Chip Select Signals ............................................................................................... 138

6.4

Basic Bus Interface ............................................................................................................ 139

6.4.1

Overview............................................................................................................... 139

6.4.2

Data Size and Data Alignment.............................................................................. 139

6.4.3

Valid Strobes......................................................................................................... 141

6.4.4

Basic Timing......................................................................................................... 142

6.4.5

Wait Control ......................................................................................................... 150

6.5

Burst ROM Interface.......................................................................................................... 152

6.5.1

Overview............................................................................................................... 152

6.5.2

Basic Timing......................................................................................................... 152

6.5.3

Wait Control ......................................................................................................... 154

6.6

Idle Cycle ........................................................................................................................... 155

6.6.1

Operation .............................................................................................................. 155

6.6.2

Pin States in Idle Cycle ......................................................................................... 158

6.7

Bus Release........................................................................................................................ 159

6.7.1

Overview............................................................................................................... 159

6.7.2

Operation .............................................................................................................. 159

6.7.3

Pin States in External Bus Released State............................................................. 160

6.7.4

Transition Timing ................................................................................................. 161

6.7.5

Usage Note............................................................................................................ 162

6.8

Bus Arbitration................................................................................................................... 162

6.8.1

Overview............................................................................................................... 162

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