H8SSLASH2214 datasheet(35/936 Pages) RENESAS

35 / 936 page

Rev.4.00 Sep. 18, 2008 Page xxxv of lx

REJ09B0189-0400

6.8.2

Operation .............................................................................................................. 162

6.8.3

Bus Transfer Timing ............................................................................................. 163

6.8.4

External Bus Release Usage Note......................................................................... 163

6.9

Resets and the Bus Controller ............................................................................................ 164

6.10

External Module Expansion Function................................................................................ 164

6.10.1 Overview............................................................................................................... 164

6.10.2 Pin Configuration.................................................................................................. 165

6.10.3 Register Configuration.......................................................................................... 165

6.10.4 Interrupt Request Input Pin Select Register 0 (IPINSEL0)................................... 166

6.10.5 External Module Connection Output Pin Select Register (OPINSEL) ................. 168

6.10.6 Module Stop Control Register B (MSTPCRB)..................................................... 170

6.10.7 Basic Timing......................................................................................................... 171

6.10.8 Notes on Use of External Module Extended Functions ........................................ 172

Section 7 DMA Controller................................................................................ 173

7.1

Overview............................................................................................................................ 173

7.1.1

Features ................................................................................................................. 173

7.1.2

Block Diagram ...................................................................................................... 174

7.1.3

Overview of Functions.......................................................................................... 175

7.1.4

Pin Configuration.................................................................................................. 177

7.1.5

7.2

7.2.1

Memory Address Register (MAR)........................................................................ 180

7.2.2

I/O Address Register (IOAR) ............................................................................... 180

7.2.3

Execute Transfer Count Register (ETCR) ............................................................ 181

7.2.4

DMA Control Register (DMACR)........................................................................ 182

7.2.5

DMA Band Control Register (DMABCR)............................................................ 186

7.3

7.3.1

Memory Address Register (MAR)........................................................................ 191

7.3.2

I/O Address Register (IOAR) ............................................................................... 191

7.3.3

Execute Transfer Count Register (ETCR) ............................................................ 192

7.3.4

DMA Control Register (DMACR)........................................................................ 194

7.3.5

DMA Band Control Register (DMABCR)............................................................ 198

7.4

Register Descriptions (3).................................................................................................... 204

7.4.1

DMA Write Enable Register (DMAWER) ........................................................... 204

7.4.2

DMA Terminal Control Register (DMATCR)...................................................... 207

7.4.3

Module Stop Control Register A (MSTPCRA) .................................................... 208

7.5

Operation............................................................................................................................ 209

7.5.1

Transfer Modes ..................................................................................................... 209

7.5.2

Sequential Mode ................................................................................................... 211

7.5.3

Idle Mode.............................................................................................................. 214

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