H8SSLASH2214 datasheet(56/936 Pages) RENESAS

56 / 936 page

Rev.4.00 Sep. 18, 2008 Page lvi of lx

REJ09B0189-0400

Table 5.10

Number of States in Interrupt Handling Routine Execution Statuses ..................... 113

Table 5.11

Interrupt Source Selection and Clearing Control .................................................... 118

Section 6 Bus Controller

Table 6.1

Bus Controller Pins ................................................................................................. 121

Table 6.2

Bus Controller Registers ......................................................................................... 122

Table 6.3

Bus Specifications for Each Area (Basic Bus Interface) ......................................... 136

Table 6.4

Data Buses Used and Valid Strobes ........................................................................ 141

Table 6.5

Pin States in Idle Cycle ........................................................................................... 158

Table 6.6

Pin States in Bus Released State ............................................................................. 160

Table 6.7

External Module Expansion Function Pins ............................................................. 165

Table 6.8

Bus Controller Registers ......................................................................................... 166

Section 7 DMA Controller

Table 7.1

Overview of DMAC Functions (Short Address Mode)........................................... 175

Table 7.2

Overview of DMAC Functions (Full Address Mode)............................................. 176

Table 7.3

DMAC Pins ............................................................................................................. 177

Table 7.4

DMAC Registers ..................................................................................................... 178

Table 7.5

Short Address Mode and Full Address Mode

(For 1 Channel: Example of Channel 0).................................................................. 179

Table 7.6

DMAC Transfer Modes .......................................................................................... 209

Table 7.7

Table 7.8

Table 7.9

Table 7.10

Table 7.11

Table 7.12

DMAC Activation Sources ..................................................................................... 230

Table 7.13

DMAC Channel Priority Order ............................................................................... 241

Table 7.14

Interrupt Source Priority Order ............................................................................... 246

Section 8 Data Transfer Controller (DTC)

Table 8.1

DTC Registers ......................................................................................................... 253

Table 8.2

DTC Functions ........................................................................................................ 263

Table 8.3

Activation Source and DTCER Clearance .............................................................. 264

Table 8.4

Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs ................. 266

Table 8.5

Table 8.6

Table 8.7

Table 8.8

DTC Execution Statuses.......................................................................................... 275

Table 8.9

Number of States Required for Each Execution Status ........................................... 276

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