H8SSLASH2214 datasheet(16/936 Pages) RENESAS

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Rev.4.00 Sep. 18, 2008 Page xvi of lx

REJ09B0189-0400

Item

Page

Revisions (See Manual for Details)

12.2.7 Serial

Status Register

(SSR)

Bit 2—Transmit End

(TEND)

470

Note added

Bit 2

TEND

Description

[Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1

• When the DMAC or DTC* is activated by a TXI interrupt and writes data to TDR

Note: * This bit is cleared by DTC when DISEL = 0 and

furthermore the transfer counter is not 0.

12.3.2 Operation in

Asynchronous Mode

Figure 12.7

Sample SCI

Initialization

Flowchart

493

Note added

Wait

Start initialization

Set data transfer format in

SMR and SCMR

[1]

Set CKE1 and CKE0 bits in SCR

(TE, RE bits 0)

Yes

Set value in BRR

Clear TE and RE bits in SCR to 0

[2]

[3]

Set TE and RE* bits in

SCR to 1, and set RIE, TIE, TEIE,

and MPIE bits

[4]

1-bit interval elapsed?

[1] Set the clock selection in SCR.

Be sure to clear bits RIE, TIE,

TEIE, and MPIE, and bits TE and

RE, to 0.

When the clock is selected in

asynchronous mode, it is output

immediately after SCR settings are

made.

[2] Set the data transfer format in SMR

and SCMR.

[3] Write a value corresponding to the

bit rate to BRR. Not necessary if an

external clock is used.

[4] Wait at least one bit interval, then

set the TE bit or RE bit in SCR to 1.

Also set the RIE, TIE, TEIE, and

MPIE bits.

Setting the TE and RE bits enables

the TxD and RxD pins to be used.

Note: * The RE bit must be set when

the RxD pin is in the 1 state. If

the RE bit is set t 1 with the

RxD pin in the 0 state, this

event may be mistakenly

recognized as a start bit.

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