H8SSLASH2214 datasheet(59/936 Pages) RENESAS

59 / 936 page

Rev.4.00 Sep. 18, 2008 Page lix of lx

REJ09B0189-0400

Table 15.10 Hardware Protection................................................................................................ 576

Table 15.11 Software Protection ................................................................................................. 577

Table 15.12 Programmer Mode Pin Settings............................................................................... 583

Table 15.13 Settings for Various Operating Modes In Programmer Mode................................. 585

Table 15.14 Programmer Mode Commands................................................................................ 586

Table 15.15 AC Characteristics in Transition to Memory Read Mode ....................................... 586

Table 15.16 AC Characteristics in Transition from Memory Read Mode to Another Mode ...... 587

Table 15.17 AC Characteristics in Memory Read Mode ............................................................ 588

Table 15.18 AC Characteristics in Auto-Program Mode ............................................................ 591

Table 15.19 AC Characteristics in Auto-Erase Mode ................................................................. 592

Table 15.20 AC Characteristics in Status Read Mode ................................................................ 594

Table 15.21 Status Read Mode Return Commands..................................................................... 595

Table 15.22 Status Polling Output Truth Table........................................................................... 595

Table 15.23 Stipulated Transition Times to Command Wait State ............................................. 596

Table 15.24 Flash Memory Operating States .............................................................................. 597

Table 15.25 Registers Present in F-ZTAT Version but Absent in Masked ROM Version ......... 604

Section 16 Clock Pulse Generator

Table 16.1

Clock Pulse Generator Register............................................................................... 606

Table 16.2

Damping Resistance Value...................................................................................... 609

Table 16.3

Crystal Resonator Parameters.................................................................................. 610

Table 16.4

External Clock Input Conditions ............................................................................. 612

Table 16.5

External Clock Input Conditions when the Duty Adjustment Circuit Is not Used .. 612

Section 17 Power-Down Modes

Table 17.1

LSI Internal States in Each Mode............................................................................ 618

Table 17.2

Power-Down Mode Registers.................................................................................. 620

Table 17.3

MSTP Bits and Corresponding On-Chip Supporting Modules ............................... 627

Table 17.4

Oscillation Stabilization Time Settings ................................................................... 630

Table 17.5

φ Pin State in Each Processing Mode...................................................................... 633

Section 18 Electrical Characteristics

Table 18.1

Absolute Maximum Ratings.................................................................................... 635

Table 18.2

DC Characteristics (1) ............................................................................................. 637

Table 18.3

DC Characteristics (2) ............................................................................................. 639

Table 18.4

DC Characteristics (3) ............................................................................................. 640

Table 18.5

Permissible Output Currents.................................................................................... 641

Table 18.6

Clock Timing........................................................................................................... 642

Table 18.7

Control Signal Timing............................................................................................. 644

Table 18.8

Bus Timing.............................................................................................................. 646

Table 18.9

Timing of On-Chip Supporting Modules ................................................................ 653

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