H8SSLASH2214 datasheet(51/936 Pages) RENESAS

51 / 936 page

Rev.4.00 Sep. 18, 2008 Page li of lx

REJ09B0189-0400

Figure 12.22 Example of SCI Operation in Transmission............................................................ 514

Figure 12.23 Sample Serial Reception Flowchart ........................................................................ 515

Figure 12.24 Example of SCI Operation in Reception ................................................................. 516

Figure 12.25 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations ........ 517

Figure 12.26 Receive Data Sampling Timing in Asynchronous Mode ........................................ 522

Figure 12.27 Example of Clocked Synchronous Transmission by DTC ...................................... 524

Figure 12.28 Sample Flowchart for Mode Transition during Transmission................................. 525

Figure 12.29 Asynchronous Transmission Using Internal Clock ................................................. 526

Figure 12.30 Synchronous Transmission Using Internal Clock ................................................... 526

Figure 12.31 Sample Flowchart for Mode Transition during Reception ...................................... 527

Figure 12.32 Operation when Switching from SCK Pin Function to Port Pin Function .............. 528

Figure 12.33 Operation when Switching from SCK Pin Function to Port Pin Function

(Example of Preventing Low-Level Output)........................................................... 529

Section 13 D/A Converter

Figure 13.1 Block Diagram of D/A Converter ........................................................................... 532

Figure 13.2 Example of D/A Converter Operation..................................................................... 537

Section 14 RAM

Figure 14.1 Block Diagram of RAM .......................................................................................... 539

Section 15 ROM

Figure 15.1 Block Diagram of ROM .......................................................................................... 543

Figure 15.2 Block Diagram of Flash Memory............................................................................ 547

Figure 15.3 Flash Memory State Transitions.............................................................................. 548

Figure 15.4 Boot Mode............................................................................................................... 549

Figure 15.5 User Program Mode ................................................................................................ 550

Figure 15.6 Reading Overlap RAM Data in User Mode or User Program Mode....................... 551

Figure 15.7 Writing Overlap RAM Data in User Program Mode............................................... 552

Figure 15.8 Flash Memory Blocks ............................................................................................. 553

Figure 15.9 System Configuration in Boot Mode....................................................................... 565

Figure 15.10 Boot Mode Execution Procedure............................................................................. 566

Figure 15.11 Automatic SCI Bit Rate Adjustment ....................................................................... 567

Figure 15.12 RAM Areas in Boot Mode ...................................................................................... 568

Figure 15.13 User Program Mode Execution Procedure .............................................................. 570

Figure 15.14 Program/Program-Verify Flowchart........................................................................ 573

Figure 15.15 Erase/Erase-Verify Flowchart ................................................................................. 575

Figure 15.16 Flash Memory State Transitions.............................................................................. 579

Figure 15.17 Flowchart for Flash Memory Emulation in RAM ................................................... 580

Figure 15.18 Example of RAM Overlap Operation...................................................................... 581

Figure 15.19 On-Chip ROM Memory Map.................................................................................. 583

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