H8SSLASH2214 datasheet(52/936 Pages) RENESAS

52 / 936 page

Rev.4.00 Sep. 18, 2008 Page lii of lx

REJ09B0189-0400

Figure 15.20 Socket Adapter Pin Correspondence Diagram ........................................................ 584

Figure 15.21 Timing Waveforms for Memory Read after Memory Write ................................... 587

Figure 15.22 Timing Waveforms in Transition from Memory Read Mode to Another Mode ..... 588

Figure 15.23

CE and OE Enable State Read Timing Waveforms ................................................ 589

Figure 15.24

CE and OE Clock System Read Timing Waveforms.............................................. 589

Figure 15.25 Auto-Program Mode Timing Waveforms ............................................................... 591

Figure 15.26 Auto-Erase Mode Timing Waveforms .................................................................... 593

Figure 15.27 Status Read Mode Timing Waveforms ................................................................... 594

Figure 15.28 Oscillation Stabilization Time, Boot Program Transfer Time,

and Power-Down Sequence..................................................................................... 596

Figure 15.29 Power-On/Off Timing (Boot Mode) ....................................................................... 601

Figure 15.30 Power-On/Off Timing (User Program Mode) ......................................................... 602

Figure 15.31 Mode Transition Timing

(Example: Boot Mode

→ User Mode ↔ User Program Mode).............................. 603

Section 16 Clock Pulse Generator

Figure 16.1 Block Diagram of Clock Pulse Generator ............................................................... 605

Figure 16.2 Connection of Crystal Resonator (Example)........................................................... 609

Figure 16.3 Crystal Resonator Equivalent Circuit ...................................................................... 609

Figure 16.4 Example of Incorrect Board Design ........................................................................ 610

Figure 16.5 External Clock Input (Examples) ............................................................................ 611

Figure 16.6 External Clock Input Timing................................................................................... 612

Figure 16.7 Example of External Clock Switching Circuit ........................................................ 613

Figure 16.8 Example of External Clock Switchover Timing...................................................... 614

Section 17 Power-Down Modes

Figure 17.1 Mode Transitions..................................................................................................... 619

Figure 17.2 Medium-Speed Mode Transition and Clearance Timing ........................................ 625

Figure 17.3 Software Standby Mode Application Example ....................................................... 631

Figure 17.4 Hardware Standby Mode Timing (Example) .......................................................... 633

Section 18 Electrical Characteristics

Figure 18.1 Power Supply Voltage and Operating Ranges ........................................................ 636

Figure 18.2 Output Load Circuit ................................................................................................ 642

Figure 18.3 System Clock Timing.............................................................................................. 643

Figure 18.4 Oscillator Settling Timing ....................................................................................... 643

Figure 18.5 Reset Input Timing.................................................................................................. 644

Figure 18.6 Interrupt Input Timing............................................................................................. 645

Figure 18.7 Basic Bus Timing/Two-State Access ...................................................................... 648

Figure 18.8 Basic Bus Timing/Three-State Access .................................................................... 649

Figure 18.9 Basic Bus Timing/Three-State Access with One Wait State................................... 650

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