H8SSLASH2214 datasheet(88/936 Pages) RENESAS

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Section 2 CPU

Rev.4.00 Sep. 18, 2008 Page 28 of 872

REJ09B0189-0400

General register ER7 has the function of stack pointer (SP) in addition to its general-register

function, and is used implicitly in exception handling and subroutine calls. Figure 2.9 shows the

stack.

Free area

Stack area

SP (ER7)

Figure 2.9 Stack

2.4.3

Control Registers

The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR),

and 8-bit condition-code register (CCR).

(1) Program Counter (PC)

This 24-bit counter indicates the address of the next instruction the CPU will execute. The length

of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored (When an

instruction is fetched, the least significant PC bit is regarded as 0).

(2) Extended Control Register (EXR)

This 8-bit register contains the trace bit (T) and interrupt mask bit (I).

Bit 7—Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed

in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is

executed.

Bits 6 to 3—Reserved: These bits are reserved. They are always read as 1.

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