H8SSLASH2214 datasheet(36/936 Pages) RENESAS

36 / 936 page

Rev.4.00 Sep. 18, 2008 Page xxxvi of lx

REJ09B0189-0400

7.5.4

Repeat Mode ......................................................................................................... 217

7.5.5

Normal Mode........................................................................................................ 221

7.5.6

Block Transfer Mode ............................................................................................ 224

7.5.7

DMAC Activation Sources ................................................................................... 230

7.5.8

Basic DMAC Bus Cycles...................................................................................... 232

7.5.9

DMAC Bus Cycles (Dual Address Mode)............................................................ 233

7.5.10 DMAC Multi-Channel Operation ......................................................................... 240

7.5.11 Relation between the DMAC, External Bus Requests, and the DTC ................... 242

7.5.12 NMI Interrupts and DMAC .................................................................................. 243

7.5.13 Forced Termination of DMAC Operation............................................................. 244

7.5.14 Clearing Full Address Mode ................................................................................. 245

7.6

Interrupts ............................................................................................................................ 246

7.7

Usage Notes ....................................................................................................................... 247

Section 8 Data Transfer Controller (DTC) ........................................................251

8.1

Overview............................................................................................................................ 251

8.1.1

Features................................................................................................................. 251

8.1.2

Block Diagram...................................................................................................... 252

8.1.3

8.2

Register Descriptions ......................................................................................................... 254

8.2.1

DTC Mode Register A (MRA) ............................................................................. 254

8.2.2

DTC Mode Register B (MRB).............................................................................. 256

8.2.3

DTC Source Address Register (SAR)................................................................... 257

8.2.4

DTC Destination Address Register (DAR)........................................................... 257

8.2.5

DTC Transfer Count Register A (CRA) ............................................................... 258

8.2.6

DTC Transfer Count Register B (CRB)................................................................ 258

8.2.7

DTC Enable Register (DTCER) ........................................................................... 259

8.2.8

DTC Vector Register (DTVECR)......................................................................... 260

8.2.9

Module Stop Control Register A (MSTPCRA) .................................................... 261

8.3

Operation ........................................................................................................................... 262

8.3.1

Overview............................................................................................................... 262

8.3.2

Activation Sources ................................................................................................ 264

8.3.3

DTC Vector Table ................................................................................................ 265

8.3.4

Location of Register Information in Address Space ............................................. 268

8.3.5

Normal Mode........................................................................................................ 269

8.3.6

Repeat Mode ......................................................................................................... 270

8.3.7

Block Transfer Mode ............................................................................................ 271

8.3.8

Chain Transfer ...................................................................................................... 273

8.3.9

Operation Timing.................................................................................................. 274

8.3.10 Number of DTC Execution States ........................................................................ 275

8.3.11 Procedures for Using DTC.................................................................................... 277

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