H8SSLASH2214 datasheet(46/936 Pages) RENESAS

46 / 936 page

Rev.4.00 Sep. 18, 2008 Page xlvi of lx

REJ09B0189-0400

Figure 4.3

Reset Sequence (Mode 4).......................................................................................... 85

Figure 4.4

Interrupt Sources and Number of Interrupts.............................................................. 87

Figure 4.5

Stack Status after Exception Handling

(Normal Modes: Not available in the H8S/2214)...................................................... 89

Figure 4.6

Stack Status after Exception Handling (Advanced Modes) ...................................... 89

Figure 4.7

Operation when SP Value Is Odd.............................................................................. 90

Section 5 Interrupt Controller

Figure 5.1

Block Diagram of Interrupt Controller...................................................................... 92

Figure 5.2

Block Diagram of Interrupts IRQn.......................................................................... 100

Figure 5.3

Timing of Setting IRQnF ........................................................................................ 100

Figure 5.4

Block Diagram of Interrupt Control Operation ....................................................... 105

Figure 5.5

Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0.. 108

Figure 5.6

Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2.. 110

Figure 5.7

Interrupt Exception Handling.................................................................................. 111

Figure 5.8

Contention between Interrupt Generation and Disabling ........................................ 114

Figure 5.9

Interrupt Control for DTC and DMAC ................................................................... 116

Section 6 Bus Controller

Figure 6.1

Block Diagram of Bus Controller ........................................................................... 120

Figure 6.2

Overview of Area Divisions.................................................................................... 134

Figure 6.3

CSn Signal Output Timing (n = 0 to 7) ................................................................... 138

Figure 6.4

Access Sizes and Data Alignment Control (8-Bit Access Space) ........................... 139

Figure 6.5

Access Sizes and Data Alignment Control (16-Bit Access Space) ......................... 140

Figure 6.6

Bus Timing for 8-Bit 2-State Access Space ............................................................ 142

Figure 6.7

Bus Timing for 8-Bit 3-State Access Space ............................................................ 143

Figure 6.8

Bus Timing for 16-Bit 2-State Access Space (Even Address Byte Access)............ 144

Figure 6.9

Bus Timing for 16-Bit 2-State Access Space (Odd Address Byte Access) ............. 145

Figure 6.10 Bus Timing for 16-Bit 2-State Access Space (Word Access) ................................. 146

Figure 6.11 Bus Timing for 16-Bit 3-State Access Space (Even Address Byte Access)............ 147

Figure 6.12 Bus Timing for 16-Bit 3-State Access Space (Odd Address Byte Access) ............. 148

Figure 6.13 Bus Timing for 16-Bit 3-State Access Space (Word Access) ................................. 149

Figure 6.14 Example of Wait State Insertion Timing................................................................. 151

Figure 6.15 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1).................. 153

Figure 6.16 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0).................. 154

Figure 6.17 Example of Idle Cycle Operation (1) ...................................................................... 155

Figure 6.18 Example of Idle Cycle Operation (2) ...................................................................... 156

Figure 6.19 Relationship between Chip Select (

CS) and Read (RD) ......................................... 157

Figure 6.20 Bus-Released State Transition Timing.................................................................... 161

Figure 6.21 Multichip Block Diagram........................................................................................ 165

Figure 6.22 Timing of External Module Area Access by DTC .................................................. 171

H8S/2214 数据表(PDF) 46 Page - Renesas Technology Corp

H8S/2214 数据表(HTML) 46 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载