H8SSLASH2214 datasheet(78/936 Pages) RENESAS

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Section 2 CPU

Rev.4.00 Sep. 18, 2008 Page 18 of 872

REJ09B0189-0400

• High-speed operation

⎯ All frequently-used instructions execute in one or two states

⎯ Maximum clock rate

: 16 MHz

⎯ 8/16/32-bit register-register add/subtract : 62.5 ns

⎯ 8 × 8-bit register-register multiply

: 750 ns

⎯ 16 ÷ 8-bit register-register divide

: 750 ns

⎯ 16 × 16-bit register-register multiply

: 1250 ns

⎯ 32 ÷ 16-bit register-register divide

: 1250 ns

• Two CPU operating modes

⎯ Normal mode*

⎯ Advanced mode

Note: * Not available in the H8S/2214 Group.

• Power-down state

⎯ Transition to power-down state by SLEEP instruction

⎯ CPU clock speed selection

2.1.2

Differences between H8S/2600 CPU and H8S/2000 CPU

The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.

• Register configuration

The MAC register is supported only by the H8S/2600 CPU.

• Basic instructions

The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the

H8S/2600 CPU.

• Number of execution states

The number of exection states of the MULXU and MULXS instructions.

Internal Operation

Instruction

Mnemonic

H8S/2600

H8S/2000

MULXU

MULXU.B Rs, Rd

MULXU.W Rs, ERd

MULXS

MULXS.B Rs, Rd

MULXS.W Rs, ERd

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