H8SSLASH2214 datasheet(45/936 Pages) RENESAS

45 / 936 page

Rev.4.00 Sep. 18, 2008 Page xlv of lx

REJ09B0189-0400

Figures

Section 1 Overview

Figure 1.1

H8S/2214 Group Internal Block Diagram................................................................... 5

Figure 1.2

H8S/2214 Group Pin Arrangement

(TFP-100B, TFP-100BV, TFP-100G, TFP-100GV: Top View)................................. 6

Figure 1.3

H8S/2214 Group Pin Arrangement

(BP-112, BP-112V, TBP-112A, TBP-112AV: Top View) ......................................... 7

Section 2 CPU

Figure 2.1

CPU Operating Modes .............................................................................................. 20

Figure 2.2

Exception Vector Table (Normal Mode)................................................................... 21

Figure 2.3

Stack Structure in Normal Mode ............................................................................... 22

Figure 2.4

Exception Vector Table (Advanced Mode)............................................................... 23

Figure 2.5

Stack Structure in Advanced Mode ........................................................................... 24

Figure 2.6

Memory Map............................................................................................................. 25

Figure 2.7

CPU Registers ........................................................................................................... 26

Figure 2.8

Usage of General Registers ....................................................................................... 27

Figure 2.9

Stack .......................................................................................................................... 28

Figure 2.10 General Register Data Formats (1)............................................................................ 31

Figure 2.11 General Register Data Formats (2)............................................................................ 32

Figure 2.12 Memory Data Formats............................................................................................... 33

Figure 2.13 Instruction Formats (Examples) ................................................................................ 47

Figure 2.14 Branch Address Specification in Memory Indirect Mode ......................................... 52

Figure 2.15 Processing States ....................................................................................................... 56

Figure 2.16 State Transitions ........................................................................................................ 57

Figure 2.17 Stack Structure after Exception Handling (Examples) .............................................. 60

Figure 2.18 On-Chip Memory Access Cycle................................................................................ 62

Figure 2.19 Pin States during On-Chip Memory Access.............................................................. 63

Figure 2.20 On-Chip Supporting Module Access Cycle .............................................................. 64

Figure 2.21 Pin States during On-Chip Supporting Module Access............................................. 65

Figure 2.22 Flowchart for Access Methods for Registers that Include Write-Only Bits .............. 69

Section 3 MCU Operating Modes

Figure 3.1

Memory Map in Each Operating Mode in the H8S/2214.......................................... 78

Section 4 Exception Handling

Figure 4.1

Exception Sources ..................................................................................................... 80

Figure 4.2

Reset Sequence (Modes 2 and 3: Not available in the H8S/2214) ............................ 84

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