H8SSLASH2214 datasheet(14/936 Pages) RENESAS

14 / 936 page

Rev.4.00 Sep. 18, 2008 Page xiv of lx

REJ09B0189-0400

Item

Page

Revisions (See Manual for Details)

9.14 Handling of

Unused Pins

358

Newly added

10.2.1 Timer

Control Register

(TCR)

Bits 4 and 3—Clock

Edge 1 and 0

(CKEG1, CKEG0)

368

Note amended

Note: Internal clock edge selection is valid when the input clock is

φ/4 or slower. This setting is ignored if the input clock is φ

/1, or when overflow/underflow of another channel is

selected. (Counting occurs on the falling edge of

φ when

φ/1 is selected.)

10.2.5 Timer

Status Register

(TSR)

Bit 3—Input

Capture/Output

Compare Flag D

(TGFD)

383

Description amended

Bit 3

TGFD

Description

[Clearing conditions]

(Initial value)

• When DTC is activated by a TGID interrupt, the DTC module MRB register DISEL

bit is 0, and furthermore the transfer counter is not 0.

• When 0 is written to TGFD after reading TGFD = 1

Bit 2—Input

Capture/Output

Compare Flag C

(TGFC)

Description amended

Bit 2

TGFC

Description

[Clearing conditions]

(Initial value)

• When DTC is activated by a TGIC interrupt, the DTC module MRB register DISEL

bit is 0, and furthermore the transfer counter is not 0.

• When 0 is written to TGFC after reading TGFC = 1

Bit 1—Input

Capture/Output

Compare Flag B

(TGFB)

384

Description amended

Bit 1

TGFB

Description

[Clearing conditions]

(Initial value)

• When DTC is activated by a TGIB interrupt, the DTC module MRB register DISEL

bit is 0, and furthermore the transfer counter is not 0.

• When 0 is written to TGFB after reading TGFB = 1

Bit 0—Input

Capture/Output

Compare Flag A

(TGFA)

Description amended

Bit 0

TGFA

Description

[Clearing conditions]

(Initial value)

• When DTC is activated by a TGIA interrupt, the DTC module MRB register DISEL

bit is 0, and furthermore the transfer counter is not 0.

• When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1

• When 0 is written to TGFA after reading TGFA = 1

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