H8SSLASH2214 datasheet(12/936 Pages) RENESAS

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Rev.4.00 Sep. 18, 2008 Page xii of lx

REJ09B0189-0400

Item

Page

Revisions (See Manual for Details)

8.3.8 Chain

Transfer

273

Description added

Figure 8.9 shows the memory map for chain transfer. The DTC

reads the start address for the register information from the DTC

vector address corresponding to the DTC activation factor. After

the data transfer completes, the CHNE bit in this register is tested,

and if it is 1, the next register information allocated sequentially is

read and a transfer is performed. This operation continues until a

data transfer for register information whose CHNE bit is 0

completes.

8.5 Usage Notes

(1) Module Stop

280

Description added

... However, 1 cannot be written in the MSTPA6 bit while the DTC

is operating. See section 17, Power-Down Modes, for details.

9.2.2 Register

Configuration

(1) Port 1 Data

Direction Register

(P1DDR)

286

Description added

... P1DDR cannot be read; if it is, an undefined value will be read.

Setting a P1DDR bit to 1 makes the corresponding port 1 pin an

output pin, while clearing the bit to 0, makes that pin an input pin.

Since this register is a write-only register, do not use bit

manipulation instructions to write to this register. See section

2.10.4, Access Methods for Registers with Write-Only Bits.

9.3.2 Register

Configuration

(1) Port 3 Data

Direction Register

(P3DDR)

297

Description added

Setting a P3DDR bit to 1 makes the corresponding port 3 pin an

output pin, while clearing the bit to 0 makes the pin an input pin.

Since this register is a write-only register, do not use bit

manipulation instructions to write to this register. See section

2.10.4, Access Methods for Registers with Write-Only Bits.

9.5.2 Register

Configuration

(1) Port 7 Data

Direction Register

(P7DDR)

309

Description added

Setting a P7DDR bit to 1 makes the corresponding port 7 pin an

output pin, while clearing the bit to 0 makes the pin an input pin.

Since this register is a write-only register, do not use bit

manipulation instructions to write to this register. See section

2.10.4, Access Methods for Registers with Write-Only Bits.

9.7.2 Register

Configuration

(1) Port A Data

Direction Register

(PADDR)

316

Description added

Bits 7 to 4 are reserved; these bits cannot be modified and will

return an undefined value if read. Since this register is a write-only

Write-Only Bits.

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