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H8S/2214 数据表(PDF) 24 Page - Renesas Technology Corp

部件名 H8S/2214
功能描述  16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series
PDF  936 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8S/2214 数据表(HTML) 24 Page - Renesas Technology Corp

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Rev.4.00 Sep. 18, 2008 Page xxiv of lx
REJ09B0189-0400
Item
Page
Revisions (See Manual for Details)
A.1 Instruction List
Table A.1 Data
Transfer Instructions
665
Note added
Addressing Mode/
Instruction Length (Bytes)
Mnemonic
LDM*
STM*
LDM @SP+,(ERm-ERn)
L
4
STM (ERm-ERn),@-SP
L
4
(@SP
ERn32,SP+4
SP)
— — — — — —
7/9/11 [1]
Repeated for each register restored
(SP-4
SP,ERn32
@SP)
— — — — — —
7/9/11 [1]
Repeated for each register saved
Operation
Condition Code
IH N Z V C
Advanced
No. of States*1
Note : The STM/LDM instructions may only be used with the ER0
to ER6 registers.
Table A.2
Arithmetic
Instructions
669
Note added
Addressing Mode/
Instruction Length (Bytes)
Mnemonic
TAS*
TAS @ERd*2
B
4
@ERd-0
→CCR set, (1)→
— —
0
—
4
(
<bit 7> of @ERd
Operation
Condition Code
IH N Z V C
Advanced
No. of States*1
Note : The TAS instruction may only be used with the ER0, ER1,
ER4, and ER5 registers.
711
Note added
Instruction
Fetch
Branch
Address
Read
Stack
Operation
Byte
Data
Access
Word
Data
Access
Internal
Operation
Instruction
Mnemonic
I
J
K
L
M
N
LDM*
4
LDM.L @SP+,
(ERn-ERn+1)
2
4
1
LDM.L @SP+,
(ERn-ERn+2)
2
6
1
LDM.L @SP+,
(ERn-ERn+3)
2
8
1
A.4 Number of
States Required for
Instruction
Execution
Table A.15
Number of Cycles in
Instruction
Execution
715
Note amended
Instruction
Fetch
Branch
Address
Read
Stack
Operation
Byte
Data
Access
Word
Data
Access
Internal
Operation
Instruction
Mnemonic
I
J
K
L
M
N
STM*
4
STM.L (ERn-ERn+1),
@-SP
2
4
1
STM.L (ERn-ERn+2),
@-SP
2
6
1
STM.L (ERn-ERn+3),
@-SP
2
8
1
TAS*
3
TAS @ERd
2
2
716
Note added
Notes : 4. The STM/LDM instructions may only be used with the
ER0 to ER6 registers.



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