H8SSLASH2214 datasheet(10/936 Pages) RENESAS

10 / 936 page

Rev.4.00 Sep. 18, 2008 Page x of lx

REJ09B0189-0400

Item

Page

Revisions (See Manual for Details)

5.3.1 External

Interrupts

Figure 5.3 Timing

of Setting IRQnF

100

Note added

Note : n = 7 to 0

5.5.1 Contention

between Interrupt

Generation and

Disabling

113

Description amended

When an interrupt enable bit is cleared to 0 to disable interrupt

requests, the disabling becomes effective after execution of the

instruction.

5.5.5 IRQ

Interrupts

115

Newly added

5.5.6 NMI Interrupt

Usage Notes

115

Newly added

6.1.2 Block

Diagram

Figure 6.1 Block

Diagram of Bus

Controller

120

Legend added

Legend:

ABWCR : Bus width control register

ASTCR: Access state control register

BCRH: Bus control register H

BCRL: Bus control register L

WCRH: Wait state control register H

WCRL: Wait state control register L

7.3.4 DMA Control

Bits 10 to 7—

Reserved

195

Description added

Although these bits are readable/writable, only 0 should be written

here.

Bit 4—Reserved

196

Description added

Although this bit is readable/writable, only 0 should be written

here.

7.3.5 DMA Band

Control Register

(DMABCR)

Bits 10 and 8—

Reserved (DTA1A,

DTA0A)

200

Description added

Reserved bits in full address mode. Read and write possible.

Although these bits are readable/writable, only 0 should be written

here.

7.5.4 Repeat Mode 217

Description amended

Repeat mode can be specified by setting the RPE bit in DMACR

to 1, and clearing the DTIE bit in DMABCRL to 0.

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