H8SSLASH2214 datasheet(20/936 Pages) RENESAS

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Rev.4.00 Sep. 18, 2008 Page xx of lx

REJ09B0189-0400

Item

Page

Revisions (See Manual for Details)

12.3.4 Operation in

Clocked

Synchronous Mode

Figure 12.21

Sample Serial

Transmission

Flowchart

512

Note added

<End>

[1]

Yes

Initialization

Start transmission

Read TDRE flag in SSR

[2]

Write transmit data to TDR and

clear TDRE flag in SSR to 0

Yes

Read TEND flag in SSR

[3]

Clear TE bit in SCR to 0

TDRE = 1

All data transmitted?

TEND = 1

[1] SCI initialization:

The TxD pin is automatically

designated as the transmit data output

pin.

[2] SCI status check and transmit data

write:

Read SSR and check that the TDRE

flag is set to 1, then write transmit data

to TDR and clear the TDRE flag to 0.

[3] Serial transmission continuation

procedure:

To continue serial transmission, be

sure to read 1 from the TDRE flag to

confirm that writing is possible, then

write data to TDR, and then clear the

TDRE flag to 0.

Checking and clearing of the TDRE

flag is automatic when the DMAC or

DTC* is activated by a transmit data

empty interrupt (TXI) request, and data

is written to TDR.

Note: * The TDRE flag is cleared

automatically by DTC only when

the DTC DISEL bit is 0 and

furthermore the transfer counter is

not 0. Therefore the CPU must

clear the TDRE flag when either

DISEL is 1 or when DISEL is 0 and

furthermore the transfer counter is

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