H8SSLASH2214 datasheet(27/936 Pages) RENESAS

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Rev.4.00 Sep. 18, 2008 Page xxvii of lx

REJ09B0189-0400

Item

Page

Revisions (See Manual for Details)

B.2 Functions

SSR0—Serial

Status Register 0

807

Note added

TDRE

R/(W)*1

RDRF

R/(W)*1

ORER

R/(W)*1

FER

R/(W)*1

PER

R/(W)*1

MPBT

R/W

TEND

MPB

Bit

Initial value

R/W

Multiprocessor Bit

[Clearing condition]

• When data with a 0 multiprocessor bit is received

[Setting condition]

• When data with a 1 multiprocessor bit is received

Multiprocessor Bit Transfer

Data with a 0 multiprocessor bit is transmitted

Data with a 1 multiprocessor bit is transmitted

Overrun Error

Receive Data Register Full

[Clearing condition]

• When 0 is written to ORER after reading ORER = 1

[Setting condition]

• When the next serial reception is completed while RDRF = 1

Transmit End

[Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1

• When the DTC*2 is activated by a TXI interrupt request and writes data to TDR

[Setting conditions]

• When the TE bit in SCR is 0

• When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit

character

Parity Error

[Clearing condition]

• When 0 is written to PER after reading PER = 1

[Setting condition]

• When, in reception, the number of 1 bits in the receive data plus

the parity bit does not match the parity setting (even or odd)

specified by the O/

E bit in SMR

Framing Error

[Clearing condition]

• When 0 is written to FER after reading FER = 1

[Setting condition]

• When the SCI checks whether the stop bit at the end of the receive

data is 1 when reception ends, and the stop bit is 0

[Clearing conditions]

• When 0 is written to RDRF after reading RDRF = 1

• When the DTC*2 is activated by an RXI interrupt request and reads data to RDR

[Setting condition]

• When serial reception ends normally and receive data is transferred from RSR

to RDR

Transmit Data Register Empty

Notes: 1. Only 0 can be written, to clear the flag.

2. Flags are only cleared when DISEL is 0 and furthermore the transfer counter is not 0.

[Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1

• When the DTC*2 is activated by a TXI interrupt request and writes data to TDR

[Setting conditions]

• When the TE bit in SCR is 0

• When data is transferred from TDR to TSR and data can be written to TDR

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